Third RISC-V PR for 8.1 * Use xl instead of mxl for disassemble * Factor out extension tests to cpu_cfg.h * disas/riscv: Add vendor extension support * disas/riscv: Add support for XVentanaCondOps * disas/riscv: Add support for XThead* instructions * Fix mstatus related problems * Fix veyron-v1 CPU properties * Fix the xlen for data address when MPRV=1 * opensbi: Upgrade from v1.2 to v1.3 * Enable 32-bit Spike OpenSBI boot testing * Support the watchdog timer of HiFive 1 rev b * Only build qemu-system-riscv$$ on rv$$ host * Add RVV registers to log * Restrict ACLINT to TCG * Add syscall riscv_hwprobe * Add support for BF16 extensions * KVM_RISCV_SET_TIMER macro is not configured correctly * Generate devicetree only after machine initialization is complete * virt: Convert fdt_load_addr to uint64_t * KVM: fixes and enhancements * Add support for the Zfa extension # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmSr+ekACgkQr3yVEwxT # gBMMGg//ZCcyH3KXB49c2KUIFO6FKYUxN9uC3giZCtuGyEH8T2yDgZVVXnxwU+Ij # +3Ej6T/ZdWMpePC9qf+xKzHWZk7Qc8Tcg+JgQbga573894yZInRwYl8HsSlEKA+Z # vlqSBPxTlp9rlDwGP/LjGljyIFqL4konk9zi3FL4ZXTF1iHUGrh/953Y3wIreEfl # KX5UznnWcgy2BqQT1vihMbM8qCVK6iryH+QZ6LiAsPMSX1rIzk8ectQryILzoIYh # bMiwCLVMyr4ZrUXjmGTF+7/WcOWwhhyfpdstf2iotKALelZtVHit0wHcty2GYQde # nvN83jJWu04DGXkPBUsqCUQXczGo1QHjJUH3RIRJzfOby/lGt4pSzHAfKA+iNUht # ikM3SdBsXMO+ogjTtTcCMb7/m2vsMoQP60VRts9Mh3YVD0cgr7RqpqRoEMugVYnr # ca8Vijf71mB+y+pq477eV1Q8BoKpr8xa1OlFkNKPC17uMD7HoDMI44QgFOgtYp10 # TMsqqyB75q6PZhSEwm63xbmH0Zpo8kSqT/E3MTtGTyPeuL8TNNNSkCmFaGYmRrbI # XEp7vG2RaDJOvDomS3nUhA5ruc8SaXd0q25q2gLYQfCsehfFqZAwuNB5xf1zS0M0 # ov1/gwaqU93t6nLbo2cCbb0plkIFKwwJ9KKjD06wJ4KPe0TGFzk= # =3XFD # -----END PGP SIGNATURE----- # gpg: Signature made Mon 10 Jul 2023 01:30:33 PM BST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20230710-1' of https://github.com/alistair23/qemu: (54 commits) riscv: Add support for the Zfa extension target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper target/riscv: update multi-letter extension KVM properties target/riscv/cpu.c: create KVM mock properties target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext() target/riscv/cpu.c: add satp_mode properties earlier target/riscv/kvm.c: add multi-letter extension KVM properties target/riscv/kvm.c: update KVM MISA bits target/riscv: add KVM specific MISA properties target/riscv/cpu: add misa_ext_info_arr[] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids() target/riscv: use KVM scratch CPUs to init KVM properties target/riscv/cpu.c: restrict 'marchid' value target/riscv/cpu.c: restrict 'mimpid' value target/riscv/cpu.c: restrict 'mvendorid' value hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set target/riscv: skip features setup for KVM CPUs ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>