diff options
| author | Madhavan Srinivasan <maddy@linux.vnet.ibm.com> | 2015-11-20 17:01:48 +0530 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2015-11-30 19:39:01 +1100 |
| commit | 7624789234cd63b671bce1b49b93b0b1c00ea407 (patch) | |
| tree | 0b77cd9ab7c23b95eca2202e03215b8c13b5641a /linux-user/s390x | |
| parent | dbdc13a1ac0bfaa9a2d7069e9e6509721ed795ee (diff) | |
target-ppc/fpu_helper: fix FPSCR_FX bit shift operation
Currently in TCG mode, updating floating exception
summary bit (FPSCR_FX) in fpscr also updates
the upper 32bits of fpscr with all 1s.
Modify the bit shift operation statement to use
1ULL instead.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'linux-user/s390x')
0 files changed, 0 insertions, 0 deletions