diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2019-02-14 18:33:00 +0000 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2019-02-14 18:33:00 +0000 |
commit | 0266c739abbed804deabb4ccde2aa449466ac3b4 (patch) | |
tree | 3c789a8bfeac4fc6f0b5b8794528facdd9a9f3c2 /linux-user/mips | |
parent | 0d3e41d5efd638a0c5682f6813b26448c3c51624 (diff) | |
parent | ba632924450faf6741d299f8feed8150a0c6f884 (diff) |
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-feb-14-2019' into staging
MIPS queue for February 14th, 2019
# gpg: Signature made Thu 14 Feb 2019 16:48:39 GMT
# gpg: using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65
* remotes/amarkovic/tags/mips-queue-feb-14-2019:
tests/tcg: target/mips: Add tests for MSA logic instructions
tests/tcg: target/mips: Add wrappers for MSA logic instructions
tests/tcg: target/mips: Add tests for MSA interleave instructions
tests/tcg: target/mips: Add wrappers for MSA interleave instructions
tests/tcg: target/mips: Add tests for MSA bit counting instructions
tests/tcg: target/mips: Add wrappers for MSA bit counting instructions
tests/tcg: target/mips: Add a header with test utilities
tests/tcg: target/mips: Add a header with test inputs
tests/tcg: target/mips: Remove an unnecessary file
target/mips: introduce MTTCG-enabled builds
hw/mips_cpc: kick a VP when putting it into Run statewq
target/mips: hold BQL in mips_vpe_wake()
hw/mips_int: hold BQL for all interrupt requests
target/mips: reimplement SC instruction emulation and use cmpxchg
target/mips: compare virtual addresses in LL/SC sequence
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'linux-user/mips')
-rw-r--r-- | linux-user/mips/cpu_loop.c | 73 |
1 files changed, 0 insertions, 73 deletions
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index d0f62ec9b6..61dc90d51c 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -392,70 +392,6 @@ static const uint8_t mips_syscall_args[] = { # undef MIPS_SYS # endif /* O32 */ -static int do_store_exclusive(CPUMIPSState *env) -{ - target_ulong addr; - target_ulong page_addr; - target_ulong val; - uint32_t val_wp = 0; - uint32_t llnewval_wp = 0; - int flags; - int segv = 0; - int reg; - int d; - int wp; - - addr = env->lladdr; - page_addr = addr & TARGET_PAGE_MASK; - start_exclusive(); - mmap_lock(); - flags = page_get_flags(page_addr); - if ((flags & PAGE_READ) == 0) { - segv = 1; - } else { - reg = env->llreg & 0x1f; - d = (env->llreg & 0x20) != 0; - wp = (env->llreg & 0x40) != 0; - if (!wp) { - if (d) { - segv = get_user_s64(val, addr); - } else { - segv = get_user_s32(val, addr); - } - } else { - segv = get_user_s32(val, addr); - segv |= get_user_s32(val_wp, addr); - llnewval_wp = env->llnewval_wp; - } - if (!segv) { - if (val != env->llval && val_wp == llnewval_wp) { - env->active_tc.gpr[reg] = 0; - } else { - if (!wp) { - if (d) { - segv = put_user_u64(env->llnewval, addr); - } else { - segv = put_user_u32(env->llnewval, addr); - } - } else { - segv = put_user_u32(env->llnewval, addr); - segv |= put_user_u32(env->llnewval_wp, addr + 4); - } - if (!segv) { - env->active_tc.gpr[reg] = 1; - } - } - } - } - env->lladdr = -1; - if (!segv) { - env->active_tc.PC += 4; - } - mmap_unlock(); - end_exclusive(); - return segv; -} - /* Break codes */ enum { BRK_OVERFLOW = 6, @@ -597,15 +533,6 @@ done_syscall: info.si_code = TARGET_TRAP_BRKPT; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case EXCP_SC: - if (do_store_exclusive(env)) { - info.si_signo = TARGET_SIGSEGV; - info.si_errno = 0; - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->active_tc.PC; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; case EXCP_DSPDIS: info.si_signo = TARGET_SIGILL; info.si_errno = 0; |