diff options
| author | Wilfred Mallawa <wilfred.mallawa@wdc.com> | 2022-01-11 17:10:25 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-21 15:52:56 +1000 |
| commit | dda94e5c66e4c48c3709acf5532c295a80845730 (patch) | |
| tree | b8a2fb51a6ab2edd00b2fc80db1c75d5fc5b174f /linux-headers/asm-riscv | |
| parent | 0df470c3886eda19afdbd5ccd5550ce794feef7b (diff) | |
hw: timer: ibex_timer: update/add reg address
The following changes:
1. Fixes the incorrectly set CTRL register address. As
per [1] https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
The CTRL register is @ 0x04.
This was found when attempting to fixup a bug where a timer_interrupt
was not serviced on TockOS-OpenTitan.
2. Adds ALERT_TEST register as documented on [1], adding repective
switch cases to error handle and later implement functionality.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20220111071025.4169189-2-alistair.francis@opensource.wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'linux-headers/asm-riscv')
0 files changed, 0 insertions, 0 deletions