diff options
author | Xiaojuan Yang <yangxiaojuan@loongson.cn> | 2022-06-06 20:43:21 +0800 |
---|---|---|
committer | Richard Henderson <richard.henderson@linaro.org> | 2022-06-06 18:10:46 +0000 |
commit | f6783e34380955e9ec0656c7b9fb8936b9733a6a (patch) | |
tree | a200209407a3613a221f546d88d3dea9dbbacb50 /include | |
parent | a8a506c3907093a064dd2d475564e677fb1bf148 (diff) |
hw/loongarch: Add LoongArch ipi interrupt support(IPI)
This patch realize the IPI interrupt controller.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-32-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/hw/intc/loongarch_ipi.h | 52 | ||||
-rw-r--r-- | include/hw/loongarch/virt.h | 2 |
2 files changed, 54 insertions, 0 deletions
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h new file mode 100644 index 0000000000..996ed7ea93 --- /dev/null +++ b/include/hw/intc/loongarch_ipi.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch ipi interrupt header files + * + * Copyright (C) 2021 Loongson Technology Corporation Limited + */ + +#ifndef HW_LOONGARCH_IPI_H +#define HW_LOONGARCH_IPI_H + +#include "hw/sysbus.h" + +/* Mainy used by iocsr read and write */ +#define SMP_IPI_MAILBOX 0x1000ULL +#define CORE_STATUS_OFF 0x0 +#define CORE_EN_OFF 0x4 +#define CORE_SET_OFF 0x8 +#define CORE_CLEAR_OFF 0xc +#define CORE_BUF_20 0x20 +#define CORE_BUF_28 0x28 +#define CORE_BUF_30 0x30 +#define CORE_BUF_38 0x38 +#define IOCSR_IPI_SEND 0x40 +#define IOCSR_MAIL_SEND 0x48 +#define IOCSR_ANY_SEND 0x158 + +/* IPI system memory address */ +#define IPI_SYSTEM_MEM 0x1fe01000 + +#define MAX_IPI_CORE_NUM 4 +#define MAX_IPI_MBX_NUM 4 + +#define TYPE_LOONGARCH_IPI "loongarch_ipi" +OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI) + +typedef struct IPICore { + uint32_t status; + uint32_t en; + uint32_t set; + uint32_t clear; + /* 64bit buf divide into 2 32bit buf */ + uint32_t buf[MAX_IPI_MBX_NUM * 2]; + qemu_irq irq; +} IPICore; + +struct LoongArchIPI { + SysBusDevice parent_obj; + MemoryRegion ipi_iocsr_mem[MAX_IPI_CORE_NUM]; + MemoryRegion ipi_system_mem[MAX_IPI_CORE_NUM]; +}; + +#endif diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 4a4bb3f51f..09a816191c 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -11,6 +11,7 @@ #include "target/loongarch/cpu.h" #include "hw/boards.h" #include "qemu/queue.h" +#include "hw/intc/loongarch_ipi.h" #define LOONGARCH_MAX_VCPUS 4 @@ -21,6 +22,7 @@ struct LoongArchMachineState { /*< private >*/ MachineState parent_obj; + IPICore ipi_core[MAX_IPI_CORE_NUM]; MemoryRegion lowmem; MemoryRegion highmem; MemoryRegion isa_io; |