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authorHao Wu <wuhaotsh@google.com>2021-01-08 11:09:41 -0800
committerPeter Maydell <peter.maydell@linaro.org>2021-01-12 21:19:02 +0000
commit0be12dc76aabda6399a28d9b5e450da2bb94cb22 (patch)
treeadafafb14699cfbbcb537eef924ed9e71305f90f /include
parentbcda710f6c44098fc828b61630449cabcce0ae55 (diff)
hw/timer: Refactor NPCM7XX Timer to use CLK clock
This patch makes NPCM7XX Timer to use a the timer clock generated by the CLK module instead of the magic number TIMER_REF_HZ. Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20210108190945.949196-3-wuhaotsh@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
-rw-r--r--include/hw/misc/npcm7xx_clk.h6
-rw-r--r--include/hw/timer/npcm7xx_timer.h1
2 files changed, 1 insertions, 6 deletions
diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
index f641f95f3e..d5c8d16ca4 100644
--- a/include/hw/misc/npcm7xx_clk.h
+++ b/include/hw/misc/npcm7xx_clk.h
@@ -21,12 +21,6 @@
#include "hw/sysbus.h"
/*
- * The reference clock frequency for the timer modules, and the SECCNT and
- * CNTR25M registers in this module, is always 25 MHz.
- */
-#define NPCM7XX_TIMER_REF_HZ (25000000)
-
-/*
* Number of registers in our device state structure. Don't change this without
* incrementing the version_id in the vmstate.
*/
diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h
index 6993fd723a..d45c051b56 100644
--- a/include/hw/timer/npcm7xx_timer.h
+++ b/include/hw/timer/npcm7xx_timer.h
@@ -101,6 +101,7 @@ struct NPCM7xxTimerCtrlState {
uint32_t tisr;
+ Clock *clock;
NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
NPCM7xxWatchdogTimer watchdog_timer;
};