aboutsummaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorVijai Kumar K <vijai@behindbytes.com>2021-04-01 23:44:57 +0530
committerAlistair Francis <alistair.francis@wdc.com>2021-05-11 20:02:06 +1000
commit8a2aca3d79f8719b9cf79fdcdfbb89bc6bdb522a (patch)
tree3d243d29afc90c883c36eaa3810664dfa37c6b22 /include
parent07f334d89d47cba59f8f47fdc8f5983234487801 (diff)
hw/riscv: Connect Shakti UART to Shakti platform
Connect one shakti uart to the shakti_c machine. Signed-off-by: Vijai Kumar K <vijai@behindbytes.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210401181457.73039-5-vijai@behindbytes.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include')
-rw-r--r--include/hw/riscv/shakti_c.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
index 8ffc2b0213..50a2b79086 100644
--- a/include/hw/riscv/shakti_c.h
+++ b/include/hw/riscv/shakti_c.h
@@ -21,6 +21,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/boards.h"
+#include "hw/char/shakti_uart.h"
#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
#define RISCV_SHAKTI_SOC(obj) \
@@ -33,6 +34,7 @@ typedef struct ShaktiCSoCState {
/*< public >*/
RISCVHartArrayState cpus;
DeviceState *plic;
+ ShaktiUartState uart;
MemoryRegion rom;
} ShaktiCSoCState;