diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-05-17 12:51:34 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-05-26 15:33:59 -0700 |
| commit | 83ec01b675a731910b3b2183091302ad31b3482b (patch) | |
| tree | aee56ad8c1d872f923d2ca1c479da3a04cb7db59 /include | |
| parent | da383e0263f7d711eddd4f050ca95fd5ab8d2a87 (diff) | |
cpu: Move CPUClass::get_crash_info to SysemuCPUOps
cpu_get_crash_info() is called on GUEST_PANICKED events,
which only occur in system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-18-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/core/cpu.h | 1 | ||||
| -rw-r--r-- | include/hw/core/sysemu-cpu-ops.h | 5 |
2 files changed, 5 insertions, 1 deletions
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index dd3f5f996e..bf7d11b14f 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -151,7 +151,6 @@ struct CPUClass { int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); - GuestPanicInformation* (*get_crash_info)(CPUState *cpu); void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); bool (*get_paging_enabled)(const CPUState *cpu); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h index 8fa98bf2a7..b9383101fc 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -17,6 +17,11 @@ */ typedef struct SysemuCPUOps { /** + * @get_crash_info: Callback for reporting guest crash information in + * GUEST_PANICKED events. + */ + GuestPanicInformation* (*get_crash_info)(CPUState *cpu); + /** * @virtio_is_big_endian: Callback to return %true if a CPU which supports * runtime configurable endianness is currently big-endian. * Non-configurable CPUs can use the default implementation of this method. |