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authorDaniel Henrique Barboza <danielhb413@gmail.com>2022-08-11 13:39:41 -0300
committerDaniel Henrique Barboza <danielhb413@gmail.com>2022-08-31 14:08:05 -0300
commitb7c1750dc440bb46ddc38dd0c391d6394db7bdb1 (patch)
treee466ae192c4c245f3959d78d2bcae47fafdfe9c0 /include
parent8ec1e4f1ef974e901b416fef6c3b38a5cc2eeffa (diff)
ppc/pnv: add phb-id/chip-id PnvPHB4RootBus properties
The same rationale provided in the PHB3 bus case applies here. Note: we could have merged both buses in a single object, like we did with the root ports, and spare some boilerplate. The reason we opted to preserve both buses objects is twofold: - there's not user side advantage in doing so. Unifying the root ports presents a clear user QOL change when we enable user created devices back. The buses objects, aside from having a different QOM name, is transparent to the user; - we leave a door opened in case we want to increase the root port limit for phb4/5 later on without having to deal with phb3 code. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20220811163950.578927-3-danielhb413@gmail.com>
Diffstat (limited to 'include')
-rw-r--r--include/hw/pci-host/pnv_phb4.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 20aa4819d3..50d4faa001 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -45,7 +45,17 @@ typedef struct PnvPhb4DMASpace {
QLIST_ENTRY(PnvPhb4DMASpace) list;
} PnvPhb4DMASpace;
+/*
+ * PHB4 PCIe Root Bus
+ */
#define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root"
+struct PnvPHB4RootBus {
+ PCIBus parent;
+
+ uint32_t chip_id;
+ uint32_t phb_id;
+};
+OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4RootBus, PNV_PHB4_ROOT_BUS)
/*
* PHB4 PCIe Host Bridge for PowerNV machines (POWER9)