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authorBin Meng <bmeng.cn@gmail.com>2019-09-06 09:20:18 -0700
committerPalmer Dabbelt <palmer@sifive.com>2019-09-17 08:42:49 -0700
commit81e94379f75c40b77d577c6bff2d7e23c9904ccf (patch)
tree64efbcc3a5751e0897174046d5feb5ce1bb7c8e4 /include
parent7b6bb66f02bc81a6bb5d90a4fe08ab9c6841a936 (diff)
riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet
In the past we did not have a model for PRCI, hence two handcrafted clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the purpose of supplying hard-coded clock frequencies. But now since we have added the PRCI support in QEMU, we don't need them any more. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'include')
-rw-r--r--include/hw/riscv/sifive_u.h3
1 files changed, 1 insertions, 2 deletions
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 5270851aa2..e4df298c23 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -77,8 +77,7 @@ enum {
enum {
SIFIVE_U_CLOCK_FREQ = 1000000000,
SIFIVE_U_HFCLK_FREQ = 33333333,
- SIFIVE_U_RTCCLK_FREQ = 1000000,
- SIFIVE_U_GEM_CLOCK_FREQ = 125000000
+ SIFIVE_U_RTCCLK_FREQ = 1000000
};
#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1