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authorChristoffer Dall <christoffer.dall@linaro.org>2015-06-02 14:56:23 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-06-02 14:56:25 +0100
commitbd204e63a7ce9d1b5c5903c9033863b179194989 (patch)
treecb5938e63dad2973ddede828ab772086caa24f33 /include
parentdfd90a87155882d92a3efa6da9afc773fd8c6796 (diff)
target-arm: Add the GICv2m to the virt board
Add a GICv2m device to the virt board to enable MSIs on the generic PCI host controller. We allocate 64 SPIs in the IRQ space for now (this can be increased/decreased later) and map the GICv2m right after the GIC in the memory map. Reviewed-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1432897270-7780-5-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
-rw-r--r--include/hw/arm/virt.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index ceec8b3664..003ef29176 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -32,6 +32,7 @@
#include "qemu-common.h"
+#define NUM_GICV2M_SPIS 64
#define NUM_VIRTIO_TRANSPORTS 32
#define ARCH_TIMER_VIRT_IRQ 11
@@ -53,6 +54,7 @@ enum {
VIRT_PCIE_MMIO,
VIRT_PCIE_PIO,
VIRT_PCIE_ECAM,
+ VIRT_GIC_V2M,
};
typedef struct MemMapEntry {