diff options
| author | Michael S. Tsirkin <mst@redhat.com> | 2018-01-11 22:01:17 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2018-01-11 22:03:50 +0200 |
| commit | acc95bc85036c443da8bf7159a77edf9f00dcd80 (patch) | |
| tree | 21965c6e60a2e29664b7685e52feacdb6a86e0bd /include | |
| parent | 880b1ffe6ec2f0ae25cc4175716227ad275e8b8a (diff) | |
| parent | 997eba28a3ed5400a80f754bf3a1c8044b75b9ff (diff) | |
Merge remote-tracking branch 'origin/master' into HEAD
Resolve conflicts around apb.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include')
81 files changed, 1741 insertions, 646 deletions
diff --git a/include/block/block.h b/include/block/block.h index c05cac57e5..9b12774ddf 100644 --- a/include/block/block.h +++ b/include/block/block.h @@ -585,7 +585,7 @@ void bdrv_io_unplug(BlockDriverState *bs); * Begin a quiesced section of all users of @bs. This is part of * bdrv_drained_begin. */ -void bdrv_parent_drained_begin(BlockDriverState *bs); +void bdrv_parent_drained_begin(BlockDriverState *bs, BdrvChild *ignore); /** * bdrv_parent_drained_end: @@ -593,7 +593,7 @@ void bdrv_parent_drained_begin(BlockDriverState *bs); * End a quiesced section of all users of @bs. This is part of * bdrv_drained_end. */ -void bdrv_parent_drained_end(BlockDriverState *bs); +void bdrv_parent_drained_end(BlockDriverState *bs, BdrvChild *ignore); /** * bdrv_drained_begin: @@ -608,12 +608,23 @@ void bdrv_parent_drained_end(BlockDriverState *bs); void bdrv_drained_begin(BlockDriverState *bs); /** + * Like bdrv_drained_begin, but recursively begins a quiesced section for + * exclusive access to all child nodes as well. + */ +void bdrv_subtree_drained_begin(BlockDriverState *bs); + +/** * bdrv_drained_end: * * End a quiescent section started by bdrv_drained_begin(). */ void bdrv_drained_end(BlockDriverState *bs); +/** + * End a quiescent section started by bdrv_subtree_drained_begin(). + */ +void bdrv_subtree_drained_end(BlockDriverState *bs); + void bdrv_add_child(BlockDriverState *parent, BlockDriverState *child, Error **errp); void bdrv_del_child(BlockDriverState *parent, BdrvChild *child, Error **errp); diff --git a/include/block/block_int.h b/include/block/block_int.h index a5482775ec..29cafa4236 100644 --- a/include/block/block_int.h +++ b/include/block/block_int.h @@ -717,6 +717,8 @@ struct BlockDriverState { /* Accessed with atomic ops. */ int quiesce_counter; + int recursive_quiesce_counter; + unsigned int write_gen; /* Current data generation */ /* Protected by reqs_lock. */ @@ -768,6 +770,9 @@ int coroutine_fn bdrv_co_pwritev(BdrvChild *child, int64_t offset, unsigned int bytes, QEMUIOVector *qiov, BdrvRequestFlags flags); +void bdrv_apply_subtree_drain(BdrvChild *child, BlockDriverState *new_parent); +void bdrv_unapply_subtree_drain(BdrvChild *child, BlockDriverState *old_parent); + int get_tmp_filename(char *filename, int size); BlockDriver *bdrv_probe_all(const uint8_t *buf, int buf_size, const char *filename); @@ -1045,7 +1050,6 @@ bool blk_dev_is_tray_open(BlockBackend *blk); bool blk_dev_is_medium_locked(BlockBackend *blk); void bdrv_set_dirty(BlockDriverState *bs, int64_t offset, int64_t bytes); -bool bdrv_requests_pending(BlockDriverState *bs); void bdrv_clear_dirty_bitmap(BdrvDirtyBitmap *bitmap, HBitmap **out); void bdrv_undo_clear_dirty_bitmap(BdrvDirtyBitmap *bitmap, HBitmap *in); diff --git a/include/block/dirty-bitmap.h b/include/block/dirty-bitmap.h index 3579a7597c..a591c27213 100644 --- a/include/block/dirty-bitmap.h +++ b/include/block/dirty-bitmap.h @@ -91,5 +91,6 @@ bool bdrv_has_changed_persistent_bitmaps(BlockDriverState *bs); BdrvDirtyBitmap *bdrv_dirty_bitmap_next(BlockDriverState *bs, BdrvDirtyBitmap *bitmap); char *bdrv_dirty_bitmap_sha256(const BdrvDirtyBitmap *bitmap, Error **errp); +int64_t bdrv_dirty_bitmap_next_zero(BdrvDirtyBitmap *bitmap, uint64_t start); #endif diff --git a/include/block/nbd.h b/include/block/nbd.h index 113c707a5e..978e443366 100644 --- a/include/block/nbd.h +++ b/include/block/nbd.h @@ -28,20 +28,20 @@ /* Handshake phase structs - this struct is passed on the wire */ -struct nbd_option { +struct NBDOption { uint64_t magic; /* NBD_OPTS_MAGIC */ uint32_t option; /* NBD_OPT_* */ uint32_t length; } QEMU_PACKED; -typedef struct nbd_option nbd_option; +typedef struct NBDOption NBDOption; -struct nbd_opt_reply { +struct NBDOptionReply { uint64_t magic; /* NBD_REP_MAGIC */ uint32_t option; /* NBD_OPT_* */ uint32_t type; /* NBD_REP_* */ uint32_t length; } QEMU_PACKED; -typedef struct nbd_opt_reply nbd_opt_reply; +typedef struct NBDOptionReply NBDOptionReply; /* Transmission phase structs * diff --git a/include/chardev/char.h b/include/chardev/char.h index 43aabccef5..778d610295 100644 --- a/include/chardev/char.h +++ b/include/chardev/char.h @@ -248,6 +248,7 @@ typedef struct ChardevClass { void (*chr_accept_input)(Chardev *chr); void (*chr_set_echo)(Chardev *chr, bool echo); void (*chr_set_fe_open)(Chardev *chr, int fe_open); + void (*chr_be_event)(Chardev *s, int event); } ChardevClass; Chardev *qemu_chardev_new(const char *id, const char *typename, diff --git a/include/disas/bfd.h b/include/disas/bfd.h index 46c7ec3376..932453750c 100644 --- a/include/disas/bfd.h +++ b/include/disas/bfd.h @@ -428,6 +428,7 @@ int print_insn_ia64 (bfd_vma, disassemble_info*); int print_insn_lm32 (bfd_vma, disassemble_info*); int print_insn_big_nios2 (bfd_vma, disassemble_info*); int print_insn_little_nios2 (bfd_vma, disassemble_info*); +int print_insn_xtensa (bfd_vma, disassemble_info*); #if 0 /* Fetch the disassembler for a given BFD, if that support is available. */ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 0f51c92adb..b37f7d8d92 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -74,8 +74,9 @@ void cpu_reloading_memory_map(void); /** * cpu_address_space_init: * @cpu: CPU to add this address space to - * @as: address space to add * @asidx: integer index of this address space + * @prefix: prefix to be used as name of address space + * @mr: the root memory region of address space * * Add the specified address space to the CPU's cpu_ases list. * The address space added with @asidx 0 is the one used for the @@ -89,7 +90,8 @@ void cpu_reloading_memory_map(void); * * Note that with KVM only one address space is supported. */ -void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx); +void cpu_address_space_init(CPUState *cpu, int asidx, + const char *prefix, MemoryRegion *mr); #endif #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 049bba86e9..54aaa61d65 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -5,7 +5,7 @@ /* Helpers for instruction counting code generation. */ -static int icount_start_insn_idx; +static TCGOp *icount_start_insn; static inline void gen_tb_start(TranslationBlock *tb) { @@ -26,8 +26,8 @@ static inline void gen_tb_start(TranslationBlock *tb) /* We emit a movi with a dummy immediate argument. Keep the insn index * of the movi so that we later (when we know the actual insn count) * can update the immediate argument with the actual insn count. */ - icount_start_insn_idx = tcg_op_buf_count(); tcg_gen_movi_i32(imm, 0xdeadbeef); + icount_start_insn = tcg_last_op(); tcg_gen_sub_i32(count, count, imm); tcg_temp_free_i32(imm); @@ -48,14 +48,11 @@ static inline void gen_tb_end(TranslationBlock *tb, int num_insns) if (tb_cflags(tb) & CF_USE_ICOUNT) { /* Update the num_insn immediate parameter now that we know * the actual insn count. */ - tcg_set_insn_param(icount_start_insn_idx, 1, num_insns); + tcg_set_insn_param(icount_start_insn, 1, num_insns); } gen_set_label(tcg_ctx->exitreq_label); tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_REQUESTED); - - /* Terminate the linked list. */ - tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].next = 0; } static inline void gen_io_start(void) diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h index 15204ab961..22381a1708 100644 --- a/include/exec/helper-gen.h +++ b/include/exec/helper-gen.h @@ -56,6 +56,16 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ tcg_gen_callN(HELPER(name), dh_retvar(ret), 5, args); \ } +#define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ + dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6)) \ +{ \ + TCGTemp *args[6] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6) }; \ + tcg_gen_callN(HELPER(name), dh_retvar(ret), 6, args); \ +} + #include "helper.h" #include "trace/generated-helpers.h" #include "trace/generated-helpers-wrappers.h" @@ -67,6 +77,7 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ #undef DEF_HELPER_FLAGS_3 #undef DEF_HELPER_FLAGS_4 #undef DEF_HELPER_FLAGS_5 +#undef DEF_HELPER_FLAGS_6 #undef GEN_HELPER #endif /* HELPER_GEN_H */ diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index 639eefdbc0..e1fd08f2ba 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -125,6 +125,8 @@ DEF_HELPER_FLAGS_4(name, 0, ret, t1, t2, t3, t4) #define DEF_HELPER_5(name, ret, t1, t2, t3, t4, t5) \ DEF_HELPER_FLAGS_5(name, 0, ret, t1, t2, t3, t4, t5) +#define DEF_HELPER_6(name, ret, t1, t2, t3, t4, t5, t6) \ + DEF_HELPER_FLAGS_6(name, 0, ret, t1, t2, t3, t4, t5, t6) /* MAX_OPC_PARAM_IARGS must be set to n if last entry is DEF_HELPER_FLAGS_n. */ diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h index 954bef85ce..74943edb13 100644 --- a/include/exec/helper-proto.h +++ b/include/exec/helper-proto.h @@ -26,6 +26,10 @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ dh_ctype(t4), dh_ctype(t5)); +#define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ +dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ + dh_ctype(t4), dh_ctype(t5), dh_ctype(t6)); + #include "helper.h" #include "trace/generated-helpers.h" #include "tcg-runtime.h" @@ -36,5 +40,6 @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ #undef DEF_HELPER_FLAGS_3 #undef DEF_HELPER_FLAGS_4 #undef DEF_HELPER_FLAGS_5 +#undef DEF_HELPER_FLAGS_6 #endif /* HELPER_PROTO_H */ diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h index b0c5bafa99..b3bdb0c399 100644 --- a/include/exec/helper-tcg.h +++ b/include/exec/helper-tcg.h @@ -39,6 +39,12 @@ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | dh_sizemask(t5, 5) }, +#define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \ + { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \ + .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ + | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ + | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) }, + #include "helper.h" #include "trace/generated-helpers.h" #include "tcg-runtime.h" @@ -50,5 +56,6 @@ #undef DEF_HELPER_FLAGS_3 #undef DEF_HELPER_FLAGS_4 #undef DEF_HELPER_FLAGS_5 +#undef DEF_HELPER_FLAGS_6 #endif /* HELPER_TCG_H */ diff --git a/include/exec/memory.h b/include/exec/memory.h index 5ed4042f87..a4cabdf44c 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1241,18 +1241,6 @@ void memory_region_set_flush_coalesced(MemoryRegion *mr); void memory_region_clear_flush_coalesced(MemoryRegion *mr); /** - * memory_region_set_global_locking: Declares the access processing requires - * QEMU's global lock. - * - * When this is invoked, accesses to the memory region will be processed while - * holding the global lock of QEMU. This is the default behavior of memory - * regions. - * - * @mr: the memory region to be updated. - */ -void memory_region_set_global_locking(MemoryRegion *mr); - -/** * memory_region_clear_global_locking: Declares that access processing does * not depend on the QEMU global lock. * diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 72be675dd6..80c8099a23 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -558,8 +558,8 @@ typedef struct Acpi20Tcpa Acpi20Tcpa; /* * TPM2 * - * Following Level 00, Rev 00.37 of specs: - * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification + * Following Version 1.2, Revision 8 of specs: + * https://trustedcomputinggroup.org/tcg-acpi-specification/ */ struct Acpi20TPM2 { ACPI_TABLE_HEADER_DEF @@ -567,6 +567,9 @@ struct Acpi20TPM2 { uint16_t reserved; uint64_t control_area_address; uint32_t start_method; + uint8_t start_method_params[12]; + uint32_t log_area_minimum_length; + uint64_t log_area_start_address; } QEMU_PACKED; typedef struct Acpi20TPM2 Acpi20TPM2; diff --git a/include/hw/acpi/acpi.h b/include/hw/acpi/acpi.h index 7b3d93cf0d..39ff512129 100644 --- a/include/hw/acpi/acpi.h +++ b/include/hw/acpi/acpi.h @@ -39,6 +39,17 @@ #define ACPI_PM2_REGISTER_WIDTH 8 #define ACPI_PM_TIMER_WIDTH 32 +/* PC-style peripherals (also used by other machines). */ +#define ACPI_PM_PROP_S3_DISABLED "disable_s3" +#define ACPI_PM_PROP_S4_DISABLED "disable_s4" +#define ACPI_PM_PROP_S4_VAL "s4_val" +#define ACPI_PM_PROP_SCI_INT "sci_int" +#define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd" +#define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd" +#define ACPI_PM_PROP_PM_IO_BASE "pm_io_base" +#define ACPI_PM_PROP_GPE0_BLK "gpe0_blk" +#define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len" + /* PM Timer ticks per second (HZ) */ #define PM_TIMER_FREQUENCY 3579545 diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h index a352c94fde..59aeb06393 100644 --- a/include/hw/acpi/ich9.h +++ b/include/hw/acpi/ich9.h @@ -63,6 +63,8 @@ typedef struct ICH9LPCPMRegs { TCOIORegs tco_regs; } ICH9LPCPMRegs; +#define ACPI_PM_PROP_TCO_ENABLED "enable_tco" + void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, bool smm_enabled, qemu_irq sci_irq); diff --git a/include/hw/acpi/ipmi.h b/include/hw/acpi/ipmi.h index ab2bb29048..c38483565c 100644 --- a/include/hw/acpi/ipmi.h +++ b/include/hw/acpi/ipmi.h @@ -9,7 +9,6 @@ #ifndef HW_ACPI_IPMI_H #define HW_ACPI_IPMI_H -#include "qemu/osdep.h" #include "hw/acpi/aml-build.h" /* diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h index d0e8e9d956..65a73714ef 100644 --- a/include/hw/arm/fsl-imx25.h +++ b/include/hw/arm/fsl-imx25.h @@ -192,7 +192,6 @@ typedef struct FslIMX25State { #define FSL_IMX25_UART5_ADDR 0x5002C000 #define FSL_IMX25_UART5_SIZE 0x4000 #define FSL_IMX25_FEC_ADDR 0x50038000 -#define FSL_IMX25_FEC_SIZE 0x4000 #define FSL_IMX25_CCM_ADDR 0x53F80000 #define FSL_IMX25_CCM_SIZE 0x4000 #define FSL_IMX25_GPT4_ADDR 0x53F84000 diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 6eff81a995..3e6fb9b7bd 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -40,6 +40,10 @@ #define XLNX_ZYNQMP_NUM_SDHCI 2 #define XLNX_ZYNQMP_NUM_SPIS 2 +#define XLNX_ZYNQMP_NUM_QSPI_BUS 2 +#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2 +#define XLNX_ZYNQMP_NUM_QSPI_FLASH 4 + #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 @@ -83,6 +87,7 @@ typedef struct XlnxZynqMPState { SysbusAHCIState sata; SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; + XlnxZynqMPQSPIPS qspi; XlnxDPState dp; XlnxDPDMAState dpdma; diff --git a/include/hw/block/block.h b/include/hw/block/block.h index f3f6e8ef02..64b9298829 100644 --- a/include/hw/block/block.h +++ b/include/hw/block/block.h @@ -72,11 +72,11 @@ static inline unsigned int get_physical_block_exp(BlockConf *conf) /* Configuration helpers */ void blkconf_serial(BlockConf *conf, char **serial); -void blkconf_geometry(BlockConf *conf, int *trans, +bool blkconf_geometry(BlockConf *conf, int *trans, unsigned cyls_max, unsigned heads_max, unsigned secs_max, Error **errp); void blkconf_blocksizes(BlockConf *conf); -void blkconf_apply_backend_options(BlockConf *conf, bool readonly, +bool blkconf_apply_backend_options(BlockConf *conf, bool readonly, bool resizable, Error **errp); /* Hard disk geometry */ diff --git a/include/hw/compat.h b/include/hw/compat.h index cf389b4e85..263de973a7 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -1,6 +1,9 @@ #ifndef HW_COMPAT_H #define HW_COMPAT_H +#define HW_COMPAT_2_11 \ + /* empty */ + #define HW_COMPAT_2_10 \ {\ .driver = "virtio-mouse-device",\ diff --git a/include/hw/cpu/core.h b/include/hw/cpu/core.h index 79ac79c29c..b7470644d8 100644 --- a/include/hw/cpu/core.h +++ b/include/hw/cpu/core.h @@ -9,7 +9,6 @@ #ifndef HW_CPU_CORE_H #define HW_CPU_CORE_H -#include "qemu/osdep.h" #include "hw/qdev.h" #define TYPE_CPU_CORE "cpu-core" diff --git a/include/hw/display/vga.h b/include/hw/display/vga.h new file mode 100644 index 0000000000..0401a3a292 --- /dev/null +++ b/include/hw/display/vga.h @@ -0,0 +1,25 @@ +/* + * QEMU VGA Emulator. + * + * Copyright (c) 2003 Fabrice Bellard + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#ifndef QEMU_HW_DISPLAY_VGA_H +#define QEMU_HW_DISPLAY_VGA_H + +#include "exec/memory.h" + +enum vga_retrace_method { + VGA_RETRACE_DUMB, + VGA_RETRACE_PRECISE +}; + +extern enum vga_retrace_method vga_retrace_method; + +int isa_vga_mm_init(hwaddr vram_base, + hwaddr ctrl_base, int it_shift, + MemoryRegion *address_space); + +#endif diff --git a/include/hw/i2c/ppc4xx_i2c.h b/include/hw/i2c/ppc4xx_i2c.h index e53042f6d4..3c603071bd 100644 --- a/include/hw/i2c/ppc4xx_i2c.h +++ b/include/hw/i2c/ppc4xx_i2c.h @@ -2,6 +2,8 @@ * PPC4xx I2C controller emulation * * Copyright (c) 2007 Jocelyn Mayer + * Copyright (c) 2012 François Revol + * Copyright (c) 2016 BALATON Zoltan * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -25,7 +27,6 @@ #ifndef PPC4XX_I2C_H #define PPC4XX_I2C_H -#include "qemu/osdep.h" #include "qemu-common.h" #include "hw/sysbus.h" #include "hw/i2c/i2c.h" @@ -56,6 +57,7 @@ typedef struct PPC4xxI2CState { uint8_t xfrcnt; uint8_t xtcntlss; uint8_t directcntl; + uint8_t intr; } PPC4xxI2CState; #endif /* PPC4XX_I2C_H */ diff --git a/include/hw/i386/apic.h b/include/hw/i386/apic.h index ea48ea9389..a9f6c0aa33 100644 --- a/include/hw/i386/apic.h +++ b/include/hw/i386/apic.h @@ -20,6 +20,7 @@ void apic_init_reset(DeviceState *s); void apic_sipi(DeviceState *s); void apic_poll_irq(DeviceState *d); void apic_designate_bsp(DeviceState *d, bool bsp); +int apic_get_highest_priority_irr(DeviceState *dev); /* pc.c */ DeviceState *cpu_get_current_apic(void); diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index ef438bd765..6f77eb0665 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -151,19 +151,6 @@ struct PCMachineClass { #define PC_MACHINE_CLASS(klass) \ OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE) -/* PC-style peripherals (also used by other machines). */ - -#define ACPI_PM_PROP_S3_DISABLED "disable_s3" -#define ACPI_PM_PROP_S4_DISABLED "disable_s4" -#define ACPI_PM_PROP_S4_VAL "s4_val" -#define ACPI_PM_PROP_SCI_INT "sci_int" -#define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd" -#define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd" -#define ACPI_PM_PROP_PM_IO_BASE "pm_io_base" -#define ACPI_PM_PROP_GPE0_BLK "gpe0_blk" -#define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len" -#define ACPI_PM_PROP_TCO_ENABLED "enable_tco" - /* parallel.c */ void parallel_hds_isa_init(ISABus *bus, int n); @@ -315,45 +302,10 @@ PCIBus *find_i440fx(void); extern PCIDevice *piix4_dev; int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); -/* vga.c */ -enum vga_retrace_method { - VGA_RETRACE_DUMB, - VGA_RETRACE_PRECISE -}; - -extern enum vga_retrace_method vga_retrace_method; - -int isa_vga_mm_init(hwaddr vram_base, - hwaddr ctrl_base, int it_shift, - MemoryRegion *address_space); - -/* ne2000.c */ -static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd) -{ - DeviceState *dev; - ISADevice *isadev; - - qemu_check_nic_model(nd, "ne2k_isa"); - - isadev = isa_try_create(bus, "ne2k_isa"); - if (!isadev) { - return false; - } - dev = DEVICE(isadev); - qdev_prop_set_uint32(dev, "iobase", base); - qdev_prop_set_uint32(dev, "irq", irq); - qdev_set_nic_properties(dev, nd); - qdev_init_nofail(dev); - return true; -} - /* pc_sysfw.c */ void pc_system_firmware_init(MemoryRegion *rom_memory, bool isapc_ram_fw); -/* pvpanic.c */ -uint16_t pvpanic_port(void); - /* acpi-build.c */ void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, const CPUArchIdList *apic_ids, GArray *entry); diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index ac7997ca8c..8bc29112e3 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -78,13 +78,15 @@ typedef struct NVICState { MemoryRegion sysregmem; MemoryRegion sysreg_ns_mem; + MemoryRegion systickmem; + MemoryRegion systick_ns_mem; MemoryRegion container; uint32_t num_irq; qemu_irq excpout; qemu_irq sysresetreq; - SysTickState systick; + SysTickState systick[M_REG_NUM_BANKS]; } NVICState; #endif diff --git a/include/hw/isa/i8259_internal.h b/include/hw/isa/i8259_internal.h index 6954b6ec5f..f742c2a726 100644 --- a/include/hw/isa/i8259_internal.h +++ b/include/hw/isa/i8259_internal.h @@ -28,6 +28,7 @@ #include "hw/hw.h" #include "hw/i386/pc.h" #include "hw/isa/isa.h" +#include "hw/intc/intc.h" typedef struct PICCommonState PICCommonState; @@ -76,8 +77,10 @@ struct PICCommonState { }; void pic_reset_common(PICCommonState *s); - ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master); - +void pic_stat_update_irq(int irq, int level); +bool pic_get_statistics(InterruptStatsProvider *obj, + uint64_t **irq_counts, unsigned int *nb_irqs); +void pic_print_info(InterruptStatsProvider *obj, Monitor *mon); #endif /* QEMU_I8259_INTERNAL_H */ diff --git a/include/hw/misc/pvpanic.h b/include/hw/misc/pvpanic.h new file mode 100644 index 0000000000..36a54e270c --- /dev/null +++ b/include/hw/misc/pvpanic.h @@ -0,0 +1,21 @@ +/* + * QEMU simulated pvpanic device. + * + * Copyright Fujitsu, Corp. 2013 + * + * Authors: + * Wen Congyang <wency@cn.fujitsu.com> + * Hu Tao <hutao@cn.fujitsu.com> + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ +#ifndef HW_MISC_PVPANIC_H +#define HW_MISC_PVPANIC_H + +#define TYPE_PVPANIC "pvpanic" + +uint16_t pvpanic_port(void); + +#endif diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h index 62ad473b05..7b3faa4019 100644 --- a/include/hw/net/imx_fec.h +++ b/include/hw/net/imx_fec.h @@ -52,6 +52,8 @@ #define ENET_TFWR 81 #define ENET_FRBR 83 #define ENET_FRSR 84 +#define ENET_TDSR1 89 +#define ENET_TDSR2 92 #define ENET_RDSR 96 #define ENET_TDSR 97 #define ENET_MRBR 98 @@ -66,6 +68,8 @@ #define ENET_FTRL 108 #define ENET_TACC 112 #define ENET_RACC 113 +#define ENET_TDAR1 121 +#define ENET_TDAR2 123 #define ENET_MIIGSK_CFGR 192 #define ENET_MIIGSK_ENR 194 #define ENET_ATCR 256 @@ -86,7 +90,6 @@ #define ENET_TCCR3 393 #define ENET_MAX 400 -#define ENET_MAX_FRAME_SIZE 2032 /* EIR and EIMR */ #define ENET_INT_HB (1 << 31) @@ -106,13 +109,18 @@ #define ENET_INT_WAKEUP (1 << 17) #define ENET_INT_TS_AVAIL (1 << 16) #define ENET_INT_TS_TIMER (1 << 15) +#define ENET_INT_TXF2 (1 << 7) +#define ENET_INT_TXB2 (1 << 6) +#define ENET_INT_TXF1 (1 << 3) +#define ENET_INT_TXB1 (1 << 2) #define ENET_INT_MAC (ENET_INT_HB | ENET_INT_BABR | ENET_INT_BABT | \ ENET_INT_GRA | ENET_INT_TXF | ENET_INT_TXB | \ ENET_INT_RXF | ENET_INT_RXB | ENET_INT_MII | \ ENET_INT_EBERR | ENET_INT_LC | ENET_INT_RL | \ ENET_INT_UN | ENET_INT_PLR | ENET_INT_WAKEUP | \ - ENET_INT_TS_AVAIL) + ENET_INT_TS_AVAIL | ENET_INT_TXF1 | \ + ENET_INT_TXB1 | ENET_INT_TXF2 | ENET_INT_TXB2) /* RDAR */ #define ENET_RDAR_RDAR (1 << 24) @@ -155,6 +163,8 @@ #define ENET_RCR_NLC (1 << 30) #define ENET_RCR_GRS (1 << 31) +#define ENET_MAX_FRAME_SIZE (1 << ENET_RCR_MAX_FL_LENGTH) + /* TCR */ #define ENET_TCR_GTS (1 << 0) #define ENET_TCR_FDEN (1 << 2) @@ -169,6 +179,8 @@ #define ENET_TWFR_TFWR_LENGTH (6) #define ENET_TWFR_STRFWD (1 << 8) +#define ENET_RACC_SHIFT16 BIT(7) + /* Buffer Descriptor. */ typedef struct { uint16_t length; @@ -231,6 +243,10 @@ typedef struct { #define ENET_BD_BDU (1 << 31) +#define ENET_TX_RING_NUM 3 + +#define FSL_IMX25_FEC_SIZE 0x4000 + typedef struct IMXFECState { /*< private >*/ SysBusDevice parent_obj; @@ -243,7 +259,9 @@ typedef struct IMXFECState { uint32_t regs[ENET_MAX]; uint32_t rx_descriptor; - uint32_t tx_descriptor; + + uint32_t tx_descriptor[ENET_TX_RING_NUM]; + uint32_t tx_ring_num; uint32_t phy_status; uint32_t phy_control; @@ -252,6 +270,9 @@ typedef struct IMXFECState { uint32_t phy_int_mask; bool is_fec; + + /* Buffer used to assemble a Tx frame */ + uint8_t frame[ENET_MAX_FRAME_SIZE]; } IMXFECState; #endif diff --git a/include/hw/net/ne2000-isa.h b/include/hw/net/ne2000-isa.h new file mode 100644 index 0000000000..ff2bed9c95 --- /dev/null +++ b/include/hw/net/ne2000-isa.h @@ -0,0 +1,33 @@ +/* + * QEMU NE2000 emulation -- isa bus windup + * + * Copyright (c) 2003-2004 Fabrice Bellard + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#include "hw/hw.h" +#include "hw/qdev.h" +#include "hw/isa/isa.h" +#include "net/net.h" + +#define TYPE_ISA_NE2000 "ne2k_isa" + +static inline ISADevice *isa_ne2000_init(ISABus *bus, int base, int irq, + NICInfo *nd) +{ + ISADevice *d; + + qemu_check_nic_model(nd, "ne2k_isa"); + + d = isa_try_create(bus, TYPE_ISA_NE2000); + if (d) { + DeviceState *dev = DEVICE(d); + + qdev_prop_set_uint32(dev, "iobase", base); + qdev_prop_set_uint32(dev, "irq", irq); + qdev_set_nic_properties(dev, nd); + qdev_init_nofail(dev); + } + return d; +} diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index b19bd55c40..604d899b1e 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -1,10 +1,54 @@ #ifndef PCI_HOST_APB_H #define PCI_HOST_APB_H -#include "qemu-common.h" +#include "hw/sparc/sun4u_iommu.h" + +#define MAX_IVEC 0x40 + +/* OBIO IVEC IRQs */ +#define OBIO_HDD_IRQ 0x20 +#define OBIO_NIC_IRQ 0x21 +#define OBIO_LPT_IRQ 0x22 +#define OBIO_FDD_IRQ 0x27 +#define OBIO_KBD_IRQ 0x29 +#define OBIO_MSE_IRQ 0x2a +#define OBIO_SER_IRQ 0x2b + +#define TYPE_APB "pbm" + +#define APB_DEVICE(obj) \ + OBJECT_CHECK(APBState, (obj), TYPE_APB) + +typedef struct APBState { + PCIHostState parent_obj; + + hwaddr special_base; + hwaddr mem_base; + MemoryRegion apb_config; + MemoryRegion pci_config; + MemoryRegion pci_mmio; + MemoryRegion pci_ioport; + uint64_t pci_irq_in; + IOMMUState *iommu; + PCIBridge *bridgeA; + PCIBridge *bridgeB; + uint32_t pci_control[16]; + uint32_t pci_irq_map[8]; + uint32_t pci_err_irq_map[4]; + uint32_t obio_irq_map[32]; + qemu_irq ivec_irqs[MAX_IVEC]; + unsigned int irq_request; + uint32_t reset_control; + unsigned int nr_resets; +} APBState; + +typedef struct PBMPCIBridge { + /*< private >*/ + PCIBridge parent_obj; +} PBMPCIBridge; + +#define TYPE_PBM_PCI_BRIDGE "pbm-bridge" +#define PBM_PCI_BRIDGE(obj) \ + OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE) -PCIBus *pci_apb_init(hwaddr special_base, - hwaddr mem_base, - qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3, - qemu_irq **pbm_irqs); #endif diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index 38470b2f0e..0fae4fc6a4 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -108,7 +108,7 @@ static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin) { sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); - return xics_get_qirq(XICS_FABRIC(spapr), phb->lsi_table[pin].irq); + return spapr_qirq(spapr, phb->lsi_table[pin].irq); } PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index); diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 59524cd42b..61896f9fd7 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -26,7 +26,7 @@ #include "hw/ppc/pnv_psi.h" #include "hw/ppc/pnv_occ.h" -#define TYPE_PNV_CHIP "powernv-chip" +#define TYPE_PNV_CHIP "pnv-chip" #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) #define PNV_CHIP_CLASS(klass) \ OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) @@ -117,9 +117,9 @@ typedef struct PnvChipClass { #define PNV_CHIP_INDEX(chip) \ (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) -#define TYPE_POWERNV_MACHINE MACHINE_TYPE_NAME("powernv") -#define POWERNV_MACHINE(obj) \ - OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE) +#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") +#define PNV_MACHINE(obj) \ + OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE) typedef struct PnvMachineState { /*< private >*/ @@ -144,7 +144,7 @@ typedef struct PnvMachineState { /* * BMC helpers */ -void pnv_bmc_populate_sensors(IPMIBmc *bmc, void *fdt); +void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); void pnv_bmc_powerdown(IPMIBmc *bmc); /* diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 38077b4796..7252e219e2 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -36,7 +36,7 @@ typedef struct PnvXScomInterface { typedef struct PnvXScomInterfaceClass { InterfaceClass parent; - int (*populate)(PnvXScomInterface *dev, void *fdt, int offset); + int (*dt_xscom)(PnvXScomInterface *dev, void *fdt, int offset); } PnvXScomInterfaceClass; /* @@ -67,7 +67,7 @@ typedef struct PnvXScomInterfaceClass { #define PNV_XSCOM_OCC_SIZE 0x6000 extern void pnv_xscom_realize(PnvChip *chip, Error **errp); -extern int pnv_xscom_populate(PnvChip *chip, void *fdt, int offset); +extern int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset); extern void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 9d21ca9bde..14757b805e 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -590,6 +590,16 @@ void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr); #define RTAS_EVENT_SCAN_RATE 1 +/* This helper should be used to encode interrupt specifiers when the related + * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, + * VIO devices, RTAS event sources and PHBs). + */ +static inline void spapr_dt_xics_irq(uint32_t *intspec, int irq, bool is_lsi) +{ + intspec[0] = cpu_to_be32(irq); + intspec[1] = is_lsi ? cpu_to_be32(1) : 0; +} + typedef struct sPAPRTCETable sPAPRTCETable; #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" @@ -707,4 +717,11 @@ void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); int spapr_vcpu_id(PowerPCCPU *cpu); PowerPCCPU *spapr_find_cpu(int vcpu_id); +int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi, + Error **errp); +int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi, + bool align, Error **errp); +void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num); +qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq); + #endif /* HW_SPAPR_H */ diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_core.h index f2d48d6a67..1129f344aa 100644 --- a/include/hw/ppc/spapr_cpu_core.h +++ b/include/hw/ppc/spapr_cpu_core.h @@ -28,7 +28,7 @@ typedef struct sPAPRCPUCore { CPUCore parent_obj; /*< public >*/ - void *threads; + PowerPCCPU **threads; int node_id; } sPAPRCPUCore; diff --git a/include/hw/ppc/spapr_vio.h b/include/hw/ppc/spapr_vio.h index 2e9685a5d9..e8b006d18f 100644 --- a/include/hw/ppc/spapr_vio.h +++ b/include/hw/ppc/spapr_vio.h @@ -87,7 +87,7 @@ static inline qemu_irq spapr_vio_qirq(VIOsPAPRDevice *dev) { sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); - return xics_get_qirq(XICS_FABRIC(spapr), dev->irq); + return spapr_qirq(spapr, dev->irq); } static inline bool spapr_vio_dma_valid(VIOsPAPRDevice *dev, uint64_t taddr, diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 2df99be111..6cebff47a7 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -181,13 +181,8 @@ typedef struct XICSFabricClass { #define XICS_IRQS_SPAPR 1024 -int spapr_ics_alloc(ICSState *ics, int irq_hint, bool lsi, Error **errp); -int spapr_ics_alloc_block(ICSState *ics, int num, bool lsi, bool align, - Error **errp); -void spapr_ics_free(ICSState *ics, int irq, int num); void spapr_dt_xics(int nr_servers, void *fdt, uint32_t phandle); -qemu_irq xics_get_qirq(XICSFabric *xi, int irq); ICPState *xics_icp_get(XICSFabric *xi, int server); /* Internal XICS interfaces */ @@ -212,4 +207,7 @@ typedef struct sPAPRMachineState sPAPRMachineState; int xics_kvm_init(sPAPRMachineState *spapr, Error **errp); void xics_spapr_init(sPAPRMachineState *spapr); +Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, + Error **errp); + #endif /* XICS_H */ diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h index 97e810eeb5..5bbfec634b 100644 --- a/include/hw/qdev-properties.h +++ b/include/hw/qdev-properties.h @@ -17,6 +17,7 @@ extern const PropertyInfo qdev_prop_int64; extern const PropertyInfo qdev_prop_size; extern const PropertyInfo qdev_prop_string; extern const PropertyInfo qdev_prop_chr; +extern const PropertyInfo qdev_prop_tpm; extern const PropertyInfo qdev_prop_ptr; extern const PropertyInfo qdev_prop_macaddr; extern const PropertyInfo qdev_prop_on_off_auto; diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h index af101d5ae6..44e0b94edf 100644 --- a/include/hw/registerfields.h +++ b/include/hw/registerfields.h @@ -11,6 +11,8 @@ #ifndef REGISTERFIELDS_H #define REGISTERFIELDS_H +#include <qemu/bitops.h> + /* Define constants for a 32 bit register */ /* This macro will define A_FOO, for the byte address of a register @@ -22,7 +24,7 @@ /* Define SHIFT, LENGTH and MASK constants for a field within a register */ -/* This macro will define FOO_BAR_MASK, FOO_BAR_SHIFT and FOO_BAR_LENGTH +/* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH * constants for field BAR in register FOO. */ #define FIELD(reg, field, shift, length) \ @@ -35,6 +37,9 @@ #define FIELD_EX32(storage, reg, field) \ extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_EX64(storage, reg, field) \ + extract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) /* Extract a field from an array of registers */ #define ARRAY_FIELD_EX32(regs, reg, field) \ @@ -52,6 +57,14 @@ d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ R_ ## reg ## _ ## field ## _LENGTH, v.v); \ d; }) +#define FIELD_DP64(storage, reg, field, val) ({ \ + struct { \ + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } v = { .v = val }; \ + uint64_t d; \ + d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH, v.v); \ + d; }) /* Deposit a field to array of registers. */ #define ARRAY_FIELD_DP32(regs, reg, field, val) \ diff --git a/include/hw/s390x/css.h b/include/hw/s390x/css.h index ab6ebe66b5..35facb47d2 100644 --- a/include/hw/s390x/css.h +++ b/include/hw/s390x/css.h @@ -248,7 +248,6 @@ int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len); void css_do_tsch_update_subch(SubchDev *sch); int css_do_stcrw(CRW *crw); void css_undo_stcrw(CRW *crw); -int css_do_tpi(IOIntCode *int_code, int lowcore); int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid, int rfmt, void *buf); void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo); @@ -272,12 +271,9 @@ extern const PropertyInfo css_devid_ro_propinfo; * default css image for it. * If @p bus_id is valid, and @p squash_mcss is false, verify that it is * not already in use, and find a free devno for it. - * If @p bus_id is not valid, and if either @p squash_mcss or @p is_virtual - * is true, find a free subchannel id and device number across all - * subchannel sets from the default css image. - * If @p bus_id is not valid, and if both @p squash_mcss and @p is_virtual - * are false, find a non-full css image and find a free subchannel id and - * device number across all subchannel sets from it. + * If @p bus_id is not valid find a free subchannel id and device number + * across all subchannel sets and all css images starting from the default + * css image. * * If either of the former actions succeed, allocate a subchannel structure, * initialise it with the bus id, subchannel id and device number, register @@ -286,8 +282,7 @@ extern const PropertyInfo css_devid_ro_propinfo; * The caller becomes owner of the returned subchannel structure and * is responsible for unregistering and freeing it. */ -SubchDev *css_create_sch(CssDevId bus_id, bool is_virtual, bool squash_mcss, - Error **errp); +SubchDev *css_create_sch(CssDevId bus_id, bool squash_mcss, Error **errp); /** Turn on css migration */ void css_register_vmstate(void); diff --git a/include/hw/sparc/sparc64.h b/include/hw/sparc/sparc64.h index ca3bb4be71..5af4344459 100644 --- a/include/hw/sparc/sparc64.h +++ b/include/hw/sparc/sparc64.h @@ -1,4 +1,6 @@ +#define IVEC_MAX 0x40 + SPARCCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr); void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level); diff --git a/include/hw/sparc/sun4m.h b/include/hw/sparc/sun4m.h deleted file mode 100644 index c557b0dd53..0000000000 --- a/include/hw/sparc/sun4m.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef SUN4M_H -#define SUN4M_H - -#include "qemu-common.h" -#include "exec/hwaddr.h" -#include "qapi/qmp/types.h" -#include "hw/sysbus.h" - -/* Devices used by sparc32 system. */ - -/* iommu.c */ -#define TYPE_SUN4M_IOMMU "sun4m-iommu" -#define SUN4M_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4M_IOMMU) - -#define TYPE_SUN4M_IOMMU_MEMORY_REGION "sun4m-iommu-memory-region" - -#define IOMMU_NREGS (4 * 4096 / 4) - -typedef struct IOMMUState { - SysBusDevice parent_obj; - - AddressSpace iommu_as; - IOMMUMemoryRegion iommu; - - MemoryRegion iomem; - uint32_t regs[IOMMU_NREGS]; - hwaddr iostart; - qemu_irq irq; - uint32_t version; -} IOMMUState; - -/* sparc32_dma.c */ -#include "hw/sparc/sparc32_dma.h" - -#endif diff --git a/include/hw/sparc/sun4m_iommu.h b/include/hw/sparc/sun4m_iommu.h new file mode 100644 index 0000000000..938937eb04 --- /dev/null +++ b/include/hw/sparc/sun4m_iommu.h @@ -0,0 +1,51 @@ +/* + * QEMU Sun4m iommu emulation + * + * Copyright (c) 2003-2005 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef SUN4M_IOMMU_H +#define SUN4M_IOMMU_H + +#include "qemu-common.h" +#include "hw/sysbus.h" + +#define IOMMU_NREGS (4 * 4096 / 4) + +typedef struct IOMMUState { + SysBusDevice parent_obj; + + AddressSpace iommu_as; + IOMMUMemoryRegion iommu; + + MemoryRegion iomem; + uint32_t regs[IOMMU_NREGS]; + hwaddr iostart; + qemu_irq irq; + uint32_t version; +} IOMMUState; + +#define TYPE_SUN4M_IOMMU "sun4m-iommu" +#define SUN4M_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4M_IOMMU) + +#define TYPE_SUN4M_IOMMU_MEMORY_REGION "sun4m-iommu-memory-region" + +#endif diff --git a/include/hw/sparc/sun4u_iommu.h b/include/hw/sparc/sun4u_iommu.h new file mode 100644 index 0000000000..a760172e8e --- /dev/null +++ b/include/hw/sparc/sun4u_iommu.h @@ -0,0 +1,50 @@ +/* + * QEMU sun4u IOMMU emulation + * + * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2012,2013 Artyom Tarasenko + * Copyright (c) 2017 Mark Cave-Ayland + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef SUN4U_IOMMU_H +#define SUN4U_IOMMU_H + +#include "qemu-common.h" +#include "hw/sysbus.h" + +#define IOMMU_NREGS 3 + +typedef struct IOMMUState { + SysBusDevice parent_obj; + + AddressSpace iommu_as; + IOMMUMemoryRegion iommu; + + MemoryRegion iomem; + uint64_t regs[IOMMU_NREGS]; +} IOMMUState; + +#define TYPE_SUN4U_IOMMU "sun4u-iommu" +#define SUN4U_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4U_IOMMU) + +#define TYPE_SUN4U_IOMMU_MEMORY_REGION "sun4u-iommu-memory-region" + +#endif diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 06aa09629d..d398a4e81c 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -26,11 +26,29 @@ #define XILINX_SPIPS_H #include "hw/ssi/ssi.h" -#include "qemu/fifo8.h" +#include "qemu/fifo32.h" +#include "hw/stream.h" typedef struct XilinxSPIPS XilinxSPIPS; #define XLNX_SPIPS_R_MAX (0x100 / 4) +#define XLNX_ZYNQMP_SPIPS_R_MAX (0x830 / 4) + +/* Bite off 4k chunks at a time */ +#define LQSPI_CACHE_SIZE 1024 + +typedef enum { + READ = 0x3, READ_4 = 0x13, + FAST_READ = 0xb, FAST_READ_4 = 0x0c, + DOR = 0x3b, DOR_4 = 0x3c, + QOR = 0x6b, QOR_4 = 0x6c, + DIOR = 0xbb, DIOR_4 = 0xbc, + QIOR = 0xeb, QIOR_4 = 0xec, + + PP = 0x2, PP_4 = 0x12, + DPP = 0xa2, + QPP = 0x32, QPP_4 = 0x34, +} FlashCMD; struct XilinxSPIPS { SysBusDevice parent_obj; @@ -45,19 +63,70 @@ struct XilinxSPIPS { uint8_t num_busses; uint8_t snoop_state; + int cmd_dummies; + uint8_t link_state; + uint8_t link_state_next; + uint8_t link_state_next_when; qemu_irq *cs_lines; + bool *cs_lines_state; SSIBus **spi; Fifo8 rx_fifo; Fifo8 tx_fifo; uint8_t num_txrx_bytes; + uint32_t rx_discard; uint32_t regs[XLNX_SPIPS_R_MAX]; + + bool man_start_com; }; +typedef struct { + XilinxSPIPS parent_obj; + + uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; + hwaddr lqspi_cached_addr; + Error *migration_blocker; + bool mmio_execution_enabled; +} XilinxQSPIPS; + +typedef struct { + XilinxQSPIPS parent_obj; + + StreamSlave *dma; + uint8_t dma_buf[4]; + int gqspi_irqline; + + uint32_t regs[XLNX_ZYNQMP_SPIPS_R_MAX]; + + /* GQSPI has seperate tx/rx fifos */ + Fifo8 rx_fifo_g; + Fifo8 tx_fifo_g; + Fifo32 fifo_g; + /* + * At the end of each generic command, misaligned extra bytes are discard + * or padded to tx and rx respectively to round it out (and avoid need for + * individual byte access. Since we use byte fifos, keep track of the + * alignment WRT to word access. + */ + uint8_t rx_fifo_g_align; + uint8_t tx_fifo_g_align; + bool man_start_com_g; +} XlnxZynqMPQSPIPS; + +typedef struct XilinxSPIPSClass { + SysBusDeviceClass parent_class; + + const MemoryRegionOps *reg_ops; + + uint32_t rx_fifo_size; + uint32_t tx_fifo_size; +} XilinxSPIPSClass; + #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" +#define TYPE_XLNX_ZYNQMP_QSPIPS "xlnx.usmp-gqspi" #define XILINX_SPIPS(obj) \ OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS) @@ -69,4 +138,7 @@ struct XilinxSPIPS { #define XILINX_QSPIPS(obj) \ OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS) +#define XLNX_ZYNQMP_QSPIPS(obj) \ + OBJECT_CHECK(XlnxZynqMPQSPIPS, (obj), TYPE_XLNX_ZYNQMP_QSPIPS) + #endif /* XILINX_SPIPS_H */ diff --git a/include/hw/timer/i8254.h b/include/hw/timer/i8254.h index 5adae9fa44..5b12eb918e 100644 --- a/include/hw/timer/i8254.h +++ b/include/hw/timer/i8254.h @@ -26,6 +26,7 @@ #define HW_I8254_H #include "hw/hw.h" +#include "hw/qdev.h" #include "hw/isa/isa.h" #define PIT_FREQ 1193182 @@ -48,8 +49,8 @@ typedef struct PITChannelInfo { #define TYPE_I8254 "isa-pit" #define TYPE_KVM_I8254 "kvm-pit" -static inline ISADevice *pit_init(ISABus *bus, int base, int isa_irq, - qemu_irq alt_irq) +static inline ISADevice *i8254_pit_init(ISABus *bus, int base, int isa_irq, + qemu_irq alt_irq) { DeviceState *dev; ISADevice *d; diff --git a/include/hw/timer/i8254_internal.h b/include/hw/timer/i8254_internal.h index dc09cc0467..c37a438f82 100644 --- a/include/hw/timer/i8254_internal.h +++ b/include/hw/timer/i8254_internal.h @@ -26,8 +26,8 @@ #define QEMU_I8254_INTERNAL_H #include "hw/hw.h" -#include "hw/i386/pc.h" #include "hw/isa/isa.h" +#include "qemu/timer.h" typedef struct PITChannelState { int count; /* can be 65536 */ diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/mc146818rtc.h index 7c8e64b203..fe6ed63f71 100644 --- a/include/hw/timer/mc146818rtc.h +++ b/include/hw/timer/mc146818rtc.h @@ -6,7 +6,8 @@ #define TYPE_MC146818_RTC "mc146818rtc" -ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq); +ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, + qemu_irq intercept_irq); void rtc_set_memory(ISADevice *dev, int addr, int val); int rtc_get_memory(ISADevice *dev, int addr); diff --git a/include/hw/unicore32/puv3.h b/include/hw/unicore32/puv3.h index 5a4839f8df..f587a1f622 100644 --- a/include/hw/unicore32/puv3.h +++ b/include/hw/unicore32/puv3.h @@ -14,16 +14,6 @@ #define PUV3_REGS_OFFSET (0x1000) /* 4K is reasonable */ -/* PKUnity System bus (AHB): 0xc0000000 - 0xedffffff (640MB) */ -#define PUV3_DMA_BASE (0xc0200000) /* AHB-4 */ - -/* PKUnity Peripheral bus (APB): 0xee000000 - 0xefffffff (128MB) */ -#define PUV3_GPIO_BASE (0xee500000) /* APB-5 */ -#define PUV3_INTC_BASE (0xee600000) /* APB-6 */ -#define PUV3_OST_BASE (0xee800000) /* APB-8 */ -#define PUV3_PM_BASE (0xeea00000) /* APB-10 */ -#define PUV3_PS2_BASE (0xeeb00000) /* APB-11 */ - /* Hardware interrupts */ #define PUV3_IRQS_NR (32) diff --git a/include/hw/usb.h b/include/hw/usb.h index eb28655270..9dd9c6f0d9 100644 --- a/include/hw/usb.h +++ b/include/hw/usb.h @@ -549,7 +549,6 @@ void usb_claim_port(USBDevice *dev, Error **errp); void usb_release_port(USBDevice *dev); void usb_device_attach(USBDevice *dev, Error **errp); int usb_device_detach(USBDevice *dev); -int usb_device_delete_addr(int busnr, int addr); void usb_check_attach(USBDevice *dev, Error **errp); static inline USBBus *usb_bus_from_device(USBDevice *d) diff --git a/include/hw/virtio/virtio-blk.h b/include/hw/virtio/virtio-blk.h index d3c8a6fa8c..5117431d96 100644 --- a/include/hw/virtio/virtio-blk.h +++ b/include/hw/virtio/virtio-blk.h @@ -39,6 +39,7 @@ struct VirtIOBlkConf uint32_t config_wce; uint32_t request_merging; uint16_t num_queues; + uint16_t queue_size; }; struct VirtIOBlockDataPlane; diff --git a/include/hw/xtensa/xtensa-isa.h b/include/hw/xtensa/xtensa-isa.h new file mode 100644 index 0000000000..353f82ba25 --- /dev/null +++ b/include/hw/xtensa/xtensa-isa.h @@ -0,0 +1,838 @@ +/* Interface definition for configurable Xtensa ISA support. + * + * Copyright (c) 2001-2013 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_LIBISA_H +#define XTENSA_LIBISA_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Version number: This is intended to help support code that works with + * versions of this library from multiple Xtensa releases. + */ + +#define XTENSA_ISA_VERSION 7000 + +/* + * This file defines the interface to the Xtensa ISA library. This + * library contains most of the ISA-specific information for a + * particular Xtensa processor. For example, the set of valid + * instructions, their opcode encodings and operand fields are all + * included here. + * + * This interface basically defines a number of abstract data types. + * + * . an instruction buffer - for holding the raw instruction bits + * . ISA info - information about the ISA as a whole + * . instruction formats - instruction size and slot structure + * . opcodes - information about individual instructions + * . operands - information about register and immediate instruction operands + * . stateOperands - information about processor state instruction operands + * . interfaceOperands - information about interface instruction operands + * . register files - register file information + * . processor states - internal processor state information + * . system registers - "special registers" and "user registers" + * . interfaces - TIE interfaces that are external to the processor + * . functional units - TIE shared functions + * + * The interface defines a set of functions to access each data type. + * With the exception of the instruction buffer, the internal + * representations of the data structures are hidden. All accesses must + * be made through the functions defined here. + */ + +typedef struct xtensa_isa_opaque { int unused; } *xtensa_isa; + + +/* + * Most of the Xtensa ISA entities (e.g., opcodes, regfiles, etc.) are + * represented here using sequential integers beginning with 0. The + * specific values are only fixed for a particular instantiation of an + * xtensa_isa structure, so these values should only be used + * internally. + */ + +typedef int xtensa_opcode; +typedef int xtensa_format; +typedef int xtensa_regfile; +typedef int xtensa_state; +typedef int xtensa_sysreg; +typedef int xtensa_interface; +typedef int xtensa_funcUnit; + + +/* Define a unique value for undefined items. */ + +#define XTENSA_UNDEFINED -1 + + +/* + * Overview of using this interface to decode/encode instructions: + * + * Each Xtensa instruction is associated with a particular instruction + * format, where the format defines a fixed number of slots for + * operations. The formats for the core Xtensa ISA have only one slot, + * but FLIX instructions may have multiple slots. Within each slot, + * there is a single opcode and some number of associated operands. + * + * The encoding and decoding functions operate on instruction buffers, + * not on the raw bytes of the instructions. The same instruction + * buffer data structure is used for both entire instructions and + * individual slots in those instructions -- the contents of a slot need + * to be extracted from or inserted into the buffer for the instruction + * as a whole. + * + * Decoding an instruction involves first finding the format, which + * identifies the number of slots, and then decoding each slot + * separately. A slot is decoded by finding the opcode and then using + * the opcode to determine how many operands there are. For example: + * + * xtensa_insnbuf_from_chars + * xtensa_format_decode + * for each slot { + * xtensa_format_get_slot + * xtensa_opcode_decode + * for each operand { + * xtensa_operand_get_field + * xtensa_operand_decode + * } + * } + * + * Encoding an instruction is roughly the same procedure in reverse: + * + * xtensa_format_encode + * for each slot { + * xtensa_opcode_encode + * for each operand { + * xtensa_operand_encode + * xtensa_operand_set_field + * } + * xtensa_format_set_slot + * } + * xtensa_insnbuf_to_chars + */ + + +/* Error handling. */ + +/* + * Error codes. The code for the most recent error condition can be + * retrieved with the "errno" function. For any result other than + * xtensa_isa_ok, an error message containing additional information + * about the problem can be retrieved using the "error_msg" function. + * The error messages are stored in an internal buffer, which should + * not be freed and may be overwritten by subsequent operations. + */ + +typedef enum xtensa_isa_status_enum { + xtensa_isa_ok = 0, + xtensa_isa_bad_format, + xtensa_isa_bad_slot, + xtensa_isa_bad_opcode, + xtensa_isa_bad_operand, + xtensa_isa_bad_field, + xtensa_isa_bad_iclass, + xtensa_isa_bad_regfile, + xtensa_isa_bad_sysreg, + xtensa_isa_bad_state, + xtensa_isa_bad_interface, + xtensa_isa_bad_funcUnit, + xtensa_isa_wrong_slot, + xtensa_isa_no_field, + xtensa_isa_out_of_memory, + xtensa_isa_buffer_overflow, + xtensa_isa_internal_error, + xtensa_isa_bad_value +} xtensa_isa_status; + +xtensa_isa_status xtensa_isa_errno(xtensa_isa isa); + +char *xtensa_isa_error_msg(xtensa_isa isa); + + + +/* Instruction buffers. */ + +typedef uint32_t xtensa_insnbuf_word; +typedef xtensa_insnbuf_word *xtensa_insnbuf; + + +/* Get the size in "insnbuf_words" of the xtensa_insnbuf array. */ + +int xtensa_insnbuf_size(xtensa_isa isa); + + +/* Allocate an xtensa_insnbuf of the right size. */ + +xtensa_insnbuf xtensa_insnbuf_alloc(xtensa_isa isa); + + +/* Release an xtensa_insnbuf. */ + +void xtensa_insnbuf_free(xtensa_isa isa, xtensa_insnbuf buf); + + +/* + * Conversion between raw memory (char arrays) and our internal + * instruction representation. This is complicated by the Xtensa ISA's + * variable instruction lengths. When converting to chars, the buffer + * must contain a valid instruction so we know how many bytes to copy; + * thus, the "to_chars" function returns the number of bytes copied or + * XTENSA_UNDEFINED on error. The "from_chars" function first reads the + * minimal number of bytes required to decode the instruction length and + * then proceeds to copy the entire instruction into the buffer; if the + * memory does not contain a valid instruction, it copies the maximum + * number of bytes required for the longest Xtensa instruction. The + * "num_chars" argument may be used to limit the number of bytes that + * can be read or written. Otherwise, if "num_chars" is zero, the + * functions may read or write past the end of the code. + */ + +int xtensa_insnbuf_to_chars(xtensa_isa isa, const xtensa_insnbuf insn, + unsigned char *cp, int num_chars); + +void xtensa_insnbuf_from_chars(xtensa_isa isa, xtensa_insnbuf insn, + const unsigned char *cp, int num_chars); + + + +/* ISA information. */ + +/* Initialize the ISA information. */ + +xtensa_isa xtensa_isa_init(void *xtensa_modules, xtensa_isa_status *errno_p, + char **error_msg_p); + + +/* Deallocate an xtensa_isa structure. */ + +void xtensa_isa_free(xtensa_isa isa); + + +/* Get the maximum instruction size in bytes. */ + +int xtensa_isa_maxlength(xtensa_isa isa); + + +/* + * Decode the length in bytes of an instruction in raw memory (not an + * insnbuf). This function reads only the minimal number of bytes + * required to decode the instruction length. Returns + * XTENSA_UNDEFINED on error. + */ + +int xtensa_isa_length_from_chars(xtensa_isa isa, const unsigned char *cp); + + +/* + * Get the number of stages in the processor's pipeline. The pipeline + * stage values returned by other functions in this library will range + * from 0 to N-1, where N is the value returned by this function. + * Note that the stage numbers used here may not correspond to the + * actual processor hardware, e.g., the hardware may have additional + * stages before stage 0. Returns XTENSA_UNDEFINED on error. + */ + +int xtensa_isa_num_pipe_stages(xtensa_isa isa); + + +/* Get the number of various entities that are defined for this processor. */ + +int xtensa_isa_num_formats(xtensa_isa isa); + +int xtensa_isa_num_opcodes(xtensa_isa isa); + +int xtensa_isa_num_regfiles(xtensa_isa isa); + +int xtensa_isa_num_states(xtensa_isa isa); + +int xtensa_isa_num_sysregs(xtensa_isa isa); + +int xtensa_isa_num_interfaces(xtensa_isa isa); + +int xtensa_isa_num_funcUnits(xtensa_isa isa); + + + +/* Instruction formats. */ + +/* Get the name of a format. Returns null on error. */ + +const char *xtensa_format_name(xtensa_isa isa, xtensa_format fmt); + + +/* + * Given a format name, return the format number. Returns + * XTENSA_UNDEFINED if the name is not a valid format. + */ + +xtensa_format xtensa_format_lookup(xtensa_isa isa, const char *fmtname); + + +/* + * Decode the instruction format from a binary instruction buffer. + * Returns XTENSA_UNDEFINED if the format is not recognized. + */ + +xtensa_format xtensa_format_decode(xtensa_isa isa, const xtensa_insnbuf insn); + + +/* + * Set the instruction format field(s) in a binary instruction buffer. + * All the other fields are set to zero. Returns non-zero on error. + */ + +int xtensa_format_encode(xtensa_isa isa, xtensa_format fmt, + xtensa_insnbuf insn); + + +/* + * Find the length (in bytes) of an instruction. Returns + * XTENSA_UNDEFINED on error. + */ + +int xtensa_format_length(xtensa_isa isa, xtensa_format fmt); + + +/* + * Get the number of slots in an instruction. Returns XTENSA_UNDEFINED + * on error. + */ + +int xtensa_format_num_slots(xtensa_isa isa, xtensa_format fmt); + + +/* + * Get the opcode for a no-op in a particular slot. + * Returns XTENSA_UNDEFINED on error. + */ + +xtensa_opcode xtensa_format_slot_nop_opcode(xtensa_isa isa, xtensa_format fmt, + int slot); + + +/* + * Get the bits for a specified slot out of an insnbuf for the + * instruction as a whole and put them into an insnbuf for that one + * slot, and do the opposite to set a slot. Return non-zero on error. + */ + +int xtensa_format_get_slot(xtensa_isa isa, xtensa_format fmt, int slot, + const xtensa_insnbuf insn, xtensa_insnbuf slotbuf); + +int xtensa_format_set_slot(xtensa_isa isa, xtensa_format fmt, int slot, + xtensa_insnbuf insn, const xtensa_insnbuf slotbuf); + + + +/* Opcode information. */ + +/* + * Translate a mnemonic name to an opcode. Returns XTENSA_UNDEFINED if + * the name is not a valid opcode mnemonic. + */ + +xtensa_opcode xtensa_opcode_lookup(xtensa_isa isa, const char *opname); + + +/* + * Decode the opcode for one instruction slot from a binary instruction + * buffer. Returns the opcode or XTENSA_UNDEFINED if the opcode is + * illegal. + */ + +xtensa_opcode xtensa_opcode_decode(xtensa_isa isa, xtensa_format fmt, int slot, + const xtensa_insnbuf slotbuf); + + +/* + * Set the opcode field(s) for an instruction slot. All other fields + * in the slot are set to zero. Returns non-zero if the opcode cannot + * be encoded. + */ + +int xtensa_opcode_encode(xtensa_isa isa, xtensa_format fmt, int slot, + xtensa_insnbuf slotbuf, xtensa_opcode opc); + + +/* Get the mnemonic name for an opcode. Returns null on error. */ + +const char *xtensa_opcode_name(xtensa_isa isa, xtensa_opcode opc); + + +/* Check various properties of opcodes. These functions return 0 if + * the condition is false, 1 if the condition is true, and + * XTENSA_UNDEFINED on error. The instructions are classified as + * follows: + * + * branch: conditional branch; may fall through to next instruction (B*) + * jump: unconditional branch (J, JX, RET*, RF*) + * loop: zero-overhead loop (LOOP*) + * call: unconditional call; control returns to next instruction (CALL*) + * + * For the opcodes that affect control flow in some way, the branch + * target may be specified by an immediate operand or it may be an + * address stored in a register. You can distinguish these by + * checking if the instruction has a PC-relative immediate + * operand. + */ + +int xtensa_opcode_is_branch(xtensa_isa isa, xtensa_opcode opc); + +int xtensa_opcode_is_jump(xtensa_isa isa, xtensa_opcode opc); + +int xtensa_opcode_is_loop(xtensa_isa isa, xtensa_opcode opc); + +int xtensa_opcode_is_call(xtensa_isa isa, xtensa_opcode opc); + + +/* + * Find the number of ordinary operands, state operands, and interface + * operands for an instruction. These return XTENSA_UNDEFINED on + * error. + */ + +int xtensa_opcode_num_operands(xtensa_isa isa, xtensa_opcode opc); + +int xtensa_opcode_num_stateOperands(xtensa_isa isa, xtensa_opcode opc); + +int xtensa_opcode_num_interfaceOperands(xtensa_isa isa, xtensa_opcode opc); + + +/* + * Get functional unit usage requirements for an opcode. Each "use" + * is identified by a <functional unit, pipeline stage> pair. The + * "num_funcUnit_uses" function returns the number of these "uses" or + * XTENSA_UNDEFINED on error. The "funcUnit_use" function returns + * a pointer to a "use" pair or null on error. + */ + +typedef struct xtensa_funcUnit_use_struct { + xtensa_funcUnit unit; + int stage; +} xtensa_funcUnit_use; + +int xtensa_opcode_num_funcUnit_uses(xtensa_isa isa, xtensa_opcode opc); + +xtensa_funcUnit_use *xtensa_opcode_funcUnit_use(xtensa_isa isa, + xtensa_opcode opc, int u); + + + +/* Operand information. */ + +/* Get the name of an operand. Returns null on error. */ + +const char *xtensa_operand_name(xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* + * Some operands are "invisible", i.e., not explicitly specified in + * assembly language. When assembling an instruction, you need not set + * the values of invisible operands, since they are either hardwired or + * derived from other field values. The values of invisible operands + * can be examined in the same way as other operands, but remember that + * an invisible operand may get its value from another visible one, so + * the entire instruction must be available before examining the + * invisible operand values. This function returns 1 if an operand is + * visible, 0 if it is invisible, or XTENSA_UNDEFINED on error. Note + * that whether an operand is visible is orthogonal to whether it is + * "implicit", i.e., whether it is encoded in a field in the + * instruction. + */ + +int xtensa_operand_is_visible(xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* + * Check if an operand is an input ('i'), output ('o'), or inout ('m') + * operand. Note: The output operand of a conditional assignment + * (e.g., movnez) appears here as an inout ('m') even if it is declared + * in the TIE code as an output ('o'); this allows the compiler to + * properly handle register allocation for conditional assignments. + * Returns 0 on error. + */ + +char xtensa_operand_inout(xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* + * Get and set the raw (encoded) value of the field for the specified + * operand. The "set" function does not check if the value fits in the + * field; that is done by the "encode" function below. Both of these + * functions return non-zero on error, e.g., if the field is not defined + * for the specified slot. + */ + +int xtensa_operand_get_field(xtensa_isa isa, xtensa_opcode opc, int opnd, + xtensa_format fmt, int slot, + const xtensa_insnbuf slotbuf, uint32_t *valp); + +int xtensa_operand_set_field(xtensa_isa isa, xtensa_opcode opc, int opnd, + xtensa_format fmt, int slot, + xtensa_insnbuf slotbuf, uint32_t val); + + +/* + * Encode and decode operands. The raw bits in the operand field may + * be encoded in a variety of different ways. These functions hide + * the details of that encoding. The result values are returned through + * the argument pointer. The return value is non-zero on error. + */ + +int xtensa_operand_encode(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp); + +int xtensa_operand_decode(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp); + + +/* + * An operand may be either a register operand or an immediate of some + * sort (e.g., PC-relative or not). The "is_register" function returns + * 0 if the operand is an immediate, 1 if it is a register, and + * XTENSA_UNDEFINED on error. The "regfile" function returns the + * regfile for a register operand, or XTENSA_UNDEFINED on error. + */ + +int xtensa_operand_is_register(xtensa_isa isa, xtensa_opcode opc, int opnd); + +xtensa_regfile xtensa_operand_regfile(xtensa_isa isa, xtensa_opcode opc, + int opnd); + + +/* + * Register operands may span multiple consecutive registers, e.g., a + * 64-bit data type may occupy two 32-bit registers. Only the first + * register is encoded in the operand field. This function specifies + * the number of consecutive registers occupied by this operand. For + * non-register operands, the return value is undefined. Returns + * XTENSA_UNDEFINED on error. + */ + +int xtensa_operand_num_regs(xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* + * Some register operands do not completely identify the register being + * accessed. For example, the operand value may be added to an internal + * state value. By definition, this implies that the corresponding + * regfile is not allocatable. Unknown registers should generally be + * treated with worst-case assumptions. The function returns 0 if the + * register value is unknown, 1 if known, and XTENSA_UNDEFINED on + * error. + */ + +int xtensa_operand_is_known_reg(xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* + * Check if an immediate operand is PC-relative. Returns 0 for register + * operands and non-PC-relative immediates, 1 for PC-relative + * immediates, and XTENSA_UNDEFINED on error. + */ + +int xtensa_operand_is_PCrelative(xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* + * For PC-relative offset operands, the interpretation of the offset may + * vary between opcodes, e.g., is it relative to the current PC or that + * of the next instruction? The following functions are defined to + * perform PC-relative relocations and to undo them (as in the + * disassembler). The "do_reloc" function takes the desired address + * value and the PC of the current instruction and sets the value to the + * corresponding PC-relative offset (which can then be encoded and + * stored into the operand field). The "undo_reloc" function takes the + * unencoded offset value and the current PC and sets the value to the + * appropriate address. The return values are non-zero on error. Note + * that these functions do not replace the encode/decode functions; the + * operands must be encoded/decoded separately and the encode functions + * are responsible for detecting invalid operand values. + */ + +int xtensa_operand_do_reloc(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp, uint32_t pc); + +int xtensa_operand_undo_reloc(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp, uint32_t pc); + + + +/* State Operands. */ + +/* + * Get the state accessed by a state operand. Returns XTENSA_UNDEFINED + * on error. + */ + +xtensa_state xtensa_stateOperand_state(xtensa_isa isa, xtensa_opcode opc, + int stOp); + + +/* + * Check if a state operand is an input ('i'), output ('o'), or inout + * ('m') operand. Returns 0 on error. + */ + +char xtensa_stateOperand_inout(xtensa_isa isa, xtensa_opcode opc, int stOp); + + + +/* Interface Operands. */ + +/* + * Get the external interface accessed by an interface operand. + * Returns XTENSA_UNDEFINED on error. + */ + +xtensa_interface xtensa_interfaceOperand_interface(xtensa_isa isa, + xtensa_opcode opc, + int ifOp); + + + +/* Register Files. */ + +/* + * Regfiles include both "real" regfiles and "views", where a view + * allows a group of adjacent registers in a real "parent" regfile to be + * viewed as a single register. A regfile view has all the same + * properties as its parent except for its (long) name, bit width, number + * of entries, and default ctype. You can use the parent function to + * distinguish these two classes. + */ + +/* + * Look up a regfile by either its name or its abbreviated "short name". + * Returns XTENSA_UNDEFINED on error. The "lookup_shortname" function + * ignores "view" regfiles since they always have the same shortname as + * their parents. + */ + +xtensa_regfile xtensa_regfile_lookup(xtensa_isa isa, const char *name); + +xtensa_regfile xtensa_regfile_lookup_shortname(xtensa_isa isa, + const char *shortname); + + +/* + * Get the name or abbreviated "short name" of a regfile. + * Returns null on error. + */ + +const char *xtensa_regfile_name(xtensa_isa isa, xtensa_regfile rf); + +const char *xtensa_regfile_shortname(xtensa_isa isa, xtensa_regfile rf); + + +/* + * Get the parent regfile of a "view" regfile. If the regfile is not a + * view, the result is the same as the input parameter. Returns + * XTENSA_UNDEFINED on error. + */ + +xtensa_regfile xtensa_regfile_view_parent(xtensa_isa isa, xtensa_regfile rf); + + +/* + * Get the bit width of a regfile or regfile view. + * Returns XTENSA_UNDEFINED on error. + */ + +int xtensa_regfile_num_bits(xtensa_isa isa, xtensa_regfile rf); + + +/* + * Get the number of regfile entries. Returns XTENSA_UNDEFINED on + * error. + */ + +int xtensa_regfile_num_entries(xtensa_isa isa, xtensa_regfile rf); + + + +/* Processor States. */ + +/* Look up a state by name. Returns XTENSA_UNDEFINED on error. */ + +xtensa_state xtensa_state_lookup(xtensa_isa isa, const char *name); + + +/* Get the name for a processor state. Returns null on error. */ + +const char *xtensa_state_name(xtensa_isa isa, xtensa_state st); + + +/* + * Get the bit width for a processor state. + * Returns XTENSA_UNDEFINED on error. + */ + +int xtensa_state_num_bits(xtensa_isa isa, xtensa_state st); + + +/* + * Check if a state is exported from the processor core. Returns 0 if + * the condition is false, 1 if the condition is true, and + * XTENSA_UNDEFINED on error. + */ + +int xtensa_state_is_exported(xtensa_isa isa, xtensa_state st); + + +/* + * Check for a "shared_or" state. Returns 0 if the condition is false, + * 1 if the condition is true, and XTENSA_UNDEFINED on error. + */ + +int xtensa_state_is_shared_or(xtensa_isa isa, xtensa_state st); + + + +/* Sysregs ("special registers" and "user registers"). */ + +/* + * Look up a register by its number and whether it is a "user register" + * or a "special register". Returns XTENSA_UNDEFINED if the sysreg does + * not exist. + */ + +xtensa_sysreg xtensa_sysreg_lookup(xtensa_isa isa, int num, int is_user); + + +/* + * Check if there exists a sysreg with a given name. + * If not, this function returns XTENSA_UNDEFINED. + */ + +xtensa_sysreg xtensa_sysreg_lookup_name(xtensa_isa isa, const char *name); + + +/* Get the name of a sysreg. Returns null on error. */ + +const char *xtensa_sysreg_name(xtensa_isa isa, xtensa_sysreg sysreg); + + +/* Get the register number. Returns XTENSA_UNDEFINED on error. */ + +int xtensa_sysreg_number(xtensa_isa isa, xtensa_sysreg sysreg); + + +/* + * Check if a sysreg is a "special register" or a "user register". + * Returns 0 for special registers, 1 for user registers and + * XTENSA_UNDEFINED on error. + */ + +int xtensa_sysreg_is_user(xtensa_isa isa, xtensa_sysreg sysreg); + + + +/* Interfaces. */ + +/* + * Find an interface by name. The return value is XTENSA_UNDEFINED if + * the specified interface is not found. + */ + +xtensa_interface xtensa_interface_lookup(xtensa_isa isa, const char *ifname); + + +/* Get the name of an interface. Returns null on error. */ + +const char *xtensa_interface_name(xtensa_isa isa, xtensa_interface intf); + + +/* + * Get the bit width for an interface. + * Returns XTENSA_UNDEFINED on error. + */ + +int xtensa_interface_num_bits(xtensa_isa isa, xtensa_interface intf); + + +/* + * Check if an interface is an input ('i') or output ('o') with respect + * to the Xtensa processor core. Returns 0 on error. + */ + +char xtensa_interface_inout(xtensa_isa isa, xtensa_interface intf); + + +/* + * Check if accessing an interface has potential side effects. + * Currently "data" interfaces have side effects and "control" + * interfaces do not. Returns 1 if there are side effects, 0 if not, + * and XTENSA_UNDEFINED on error. + */ + +int xtensa_interface_has_side_effect(xtensa_isa isa, xtensa_interface intf); + + +/* + * Some interfaces may be related such that accessing one interface + * has side effects on a set of related interfaces. The interfaces + * are partitioned into equivalence classes of related interfaces, and + * each class is assigned a unique identifier number. This function + * returns the class identifier for an interface, or XTENSA_UNDEFINED + * on error. These identifiers can be compared to determine if two + * interfaces are related; the specific values of the identifiers have + * no particular meaning otherwise. + */ + +int xtensa_interface_class_id(xtensa_isa isa, xtensa_interface intf); + + +/* Functional Units. */ + +/* + * Find a functional unit by name. The return value is XTENSA_UNDEFINED if + * the specified unit is not found. + */ + +xtensa_funcUnit xtensa_funcUnit_lookup(xtensa_isa isa, const char *fname); + + +/* Get the name of a functional unit. Returns null on error. */ + +const char *xtensa_funcUnit_name(xtensa_isa isa, xtensa_funcUnit fun); + + +/* + * Functional units may be replicated. See how many instances of a + * particular function unit exist. Returns XTENSA_UNDEFINED on error. + */ + +int xtensa_funcUnit_num_copies(xtensa_isa isa, xtensa_funcUnit fun); + + +#ifdef __cplusplus +} +#endif +#endif /* XTENSA_LIBISA_H */ diff --git a/include/io/net-listener.h b/include/io/net-listener.h new file mode 100644 index 0000000000..56d6da7a76 --- /dev/null +++ b/include/io/net-listener.h @@ -0,0 +1,174 @@ +/* + * QEMU network listener + * + * Copyright (c) 2016-2017 Red Hat, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see <http://www.gnu.org/licenses/>. + * + */ + +#ifndef QIO_NET_LISTENER_H +#define QIO_NET_LISTENER_H + +#include "io/channel-socket.h" + +#define TYPE_QIO_NET_LISTENER "qio-net-listener" +#define QIO_NET_LISTENER(obj) \ + OBJECT_CHECK(QIONetListener, (obj), TYPE_QIO_NET_LISTENER) +#define QIO_NET_LISTENER_CLASS(klass) \ + OBJECT_CLASS_CHECK(QIONetListenerClass, klass, TYPE_QIO_NET_LISTENER) +#define QIO_NET_LISTENER_GET_CLASS(obj) \ + OBJECT_GET_CLASS(QIONetListenerClass, obj, TYPE_QIO_NET_LISTENER) + +typedef struct QIONetListener QIONetListener; +typedef struct QIONetListenerClass QIONetListenerClass; + +typedef void (*QIONetListenerClientFunc)(QIONetListener *listener, + QIOChannelSocket *sioc, + gpointer data); + +/** + * QIONetListener: + * + * The QIONetListener object encapsulates the management of a + * listening socket. It is able to listen on multiple sockets + * concurrently, to deal with the scenario where IPv4 / IPv6 + * needs separate sockets, or there is a need to listen on a + * subset of interface IP addresses, instead of the wildcard + * address. + */ +struct QIONetListener { + Object parent; + + char *name; + QIOChannelSocket **sioc; + gulong *io_tag; + size_t nsioc; + + bool connected; + + QIONetListenerClientFunc io_func; + gpointer io_data; + GDestroyNotify io_notify; +}; + +struct QIONetListenerClass { + ObjectClass parent; +}; + + +/** + * qio_net_listener_new: + * + * Create a new network listener service, which is not + * listening on any sockets initially. + * + * Returns: the new listener + */ +QIONetListener *qio_net_listener_new(void); + + +/** + * qio_net_listener_set_name: + * @listener: the network listener object + * @name: the listener name + * + * Set the name of the listener. This is used as a debugging + * aid, to set names on any GSource instances associated + * with the listener + */ +void qio_net_listener_set_name(QIONetListener *listener, + const char *name); + +/** + * qio_net_listener_open_sync: + * @listener: the network listener object + * @addr: the address to listen on + * @errp: pointer to a NULL initialized error object + * + * Synchronously open a listening connection on all + * addresses associated with @addr. This method may + * also be invoked multiple times, in order to have a + * single listener on multiple distinct addresses. + */ +int qio_net_listener_open_sync(QIONetListener *listener, + SocketAddress *addr, + Error **errp); + +/** + * qio_net_listener_add: + * @listener: the network listener object + * @sioc: the socket I/O channel + * + * Associate a listening socket I/O channel with the + * listener. The listener will acquire a new reference + * on @sioc, so the caller should release its own reference + * if it no longer requires the object. + */ +void qio_net_listener_add(QIONetListener *listener, + QIOChannelSocket *sioc); + +/** + * qio_net_listener_set_client_func: + * @listener: the network listener object + * @func: the callback function + * @data: opaque data to pass to @func + * @notify: callback to free @data + * + * Register @func to be invoked whenever a new client + * connects to the listener. @func will be invoked + * passing in the QIOChannelSocket instance for the + * client. + */ +void qio_net_listener_set_client_func(QIONetListener *listener, + QIONetListenerClientFunc func, + gpointer data, + GDestroyNotify notify); + +/** + * qio_net_listener_wait_client: + * @listener: the network listener object + * + * Block execution of the caller until a new client arrives + * on one of the listening sockets. If there was previously + * a callback registered with qio_net_listener_set_client_func + * it will be temporarily disabled, and re-enabled afterwards. + * + * Returns: the new client socket + */ +QIOChannelSocket *qio_net_listener_wait_client(QIONetListener *listener); + + +/** + * qio_net_listener_disconnect: + * @listener: the network listener object + * + * Disconnect the listener, removing all I/O callback + * watches and closing the socket channels. + */ +void qio_net_listener_disconnect(QIONetListener *listener); + + +/** + * qio_net_listener_is_connected: + * @listener: the network listener object + * + * Determine if the listener is connected to any socket + * channels + * + * Returns: true if connected, false otherwise + */ +bool qio_net_listener_is_connected(QIONetListener *listener); + +#endif /* QIO_NET_LISTENER_H */ diff --git a/include/net/net.h b/include/net/net.h index 1c55a93588..4afac1a9dd 100644 --- a/include/net/net.h +++ b/include/net/net.h @@ -227,7 +227,10 @@ NetClientState *net_hub_port_find(int hub_id); void qdev_set_nic_properties(DeviceState *dev, NICInfo *nd); -#define POLYNOMIAL 0x04c11db6 +#define POLYNOMIAL_BE 0x04c11db6 +#define POLYNOMIAL_LE 0xedb88320 +uint32_t net_crc32(const uint8_t *p, int len); +uint32_t net_crc32_le(const uint8_t *p, int len); unsigned compute_mcast_idx(const uint8_t *ep); #define vmstate_offset_macaddr(_state, _field) \ diff --git a/include/net/slirp.h b/include/net/slirp.h index 64b795cda9..0c98e463db 100644 --- a/include/net/slirp.h +++ b/include/net/slirp.h @@ -36,8 +36,6 @@ void hmp_hostfwd_remove(Monitor *mon, const QDict *qdict); int net_slirp_redir(const char *redir_str); -int net_slirp_parse_legacy(QemuOptsList *opts_list, const char *optarg, int *ret); - int net_slirp_smb(const char *exported_dir); void hmp_info_usernet(Monitor *mon, const QDict *qdict); diff --git a/include/qemu/coroutine.h b/include/qemu/coroutine.h index 9aff9a735e..ce2eb73670 100644 --- a/include/qemu/coroutine.h +++ b/include/qemu/coroutine.h @@ -261,12 +261,8 @@ void qemu_co_rwlock_unlock(CoRwlock *lock); /** * Yield the coroutine for a given duration - * - * Behaves similarly to co_sleep_ns(), but the sleeping coroutine will be - * resumed when using aio_poll(). */ -void coroutine_fn co_aio_sleep_ns(AioContext *ctx, QEMUClockType type, - int64_t ns); +void coroutine_fn qemu_co_sleep_ns(QEMUClockType type, int64_t ns); /** * Yield until a file descriptor becomes readable diff --git a/include/qemu/hbitmap.h b/include/qemu/hbitmap.h index 81e78043d1..6b6490ecad 100644 --- a/include/qemu/hbitmap.h +++ b/include/qemu/hbitmap.h @@ -292,6 +292,14 @@ void hbitmap_iter_init(HBitmapIter *hbi, const HBitmap *hb, uint64_t first); */ unsigned long hbitmap_iter_skip_words(HBitmapIter *hbi); +/* hbitmap_next_zero: + * @hb: The HBitmap to operate on + * @start: The bit to start from. + * + * Find next not dirty bit. + */ +int64_t hbitmap_next_zero(const HBitmap *hb, uint64_t start); + /* hbitmap_create_meta: * Create a "meta" hbitmap to track dirtiness of the bits in this HBitmap. * The caller owns the created bitmap and must call hbitmap_free_meta(hb) to diff --git a/include/qemu/option.h b/include/qemu/option.h index f7338dbe80..a88c5f02b1 100644 --- a/include/qemu/option.h +++ b/include/qemu/option.h @@ -31,11 +31,6 @@ const char *get_opt_name(char *buf, int buf_size, const char *p, char delim); const char *get_opt_value(char *buf, int buf_size, const char *p); -int get_next_param_value(char *buf, int buf_size, - const char *tag, const char **pstr); -int get_param_value(char *buf, int buf_size, - const char *tag, const char *str); - void parse_option_size(const char *name, const char *value, uint64_t *ret, Error **errp); diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index e8568a0a54..adb3758275 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -365,6 +365,9 @@ void qemu_anon_ram_free(void *ptr, size_t size); #elif defined(__linux__) && defined(__s390x__) /* Use 1 MiB (segment size) alignment so gmap can be used by KVM. */ # define QEMU_VMALLOC_ALIGN (256 * 4096) +#elif defined(__linux__) && defined(__sparc__) +#include <sys/shm.h> +# define QEMU_VMALLOC_ALIGN MAX(getpagesize(), SHMLBA) #else # define QEMU_VMALLOC_ALIGN getpagesize() #endif diff --git a/include/qemu/qht.h b/include/qemu/qht.h index 56c2c7784c..531aa95325 100644 --- a/include/qemu/qht.h +++ b/include/qemu/qht.h @@ -166,7 +166,7 @@ void qht_iter(struct qht *ht, qht_iter_func_t func, void *userp); /** * qht_statistics_init - Gather statistics from a QHT * @ht: QHT to gather statistics from - * @stats: pointer to a struct qht_stats to be filled in + * @stats: pointer to a &struct qht_stats to be filled in * * Does NOT need to be called under an RCU read-critical section, * since it does not dereference any pointers stored in the hash table. @@ -177,8 +177,8 @@ void qht_iter(struct qht *ht, qht_iter_func_t func, void *userp); void qht_statistics_init(struct qht *ht, struct qht_stats *stats); /** - * qht_statistics_destroy - Destroy a struct qht_stats - * @stats: stuct qht_stats to be destroyed + * qht_statistics_destroy - Destroy a &struct qht_stats + * @stats: &struct qht_stats to be destroyed * * See also: qht_statistics_init(). */ diff --git a/include/qemu/queue.h b/include/qemu/queue.h index 35292c3155..aa270d2b38 100644 --- a/include/qemu/queue.h +++ b/include/qemu/queue.h @@ -425,6 +425,11 @@ struct { \ (var); \ (var) = (*(((struct headname *)((var)->field.tqe_prev))->tqh_last))) +#define QTAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, prev_var) \ + for ((var) = (*(((struct headname *)((head)->tqh_last))->tqh_last)); \ + (var) && ((prev_var) = (*(((struct headname *)((var)->field.tqe_prev))->tqh_last)), 1); \ + (var) = (prev_var)) + /* * Tail queue access methods. */ diff --git a/include/qemu/sockets.h b/include/qemu/sockets.h index 4f7311b52a..8889bcb1ec 100644 --- a/include/qemu/sockets.h +++ b/include/qemu/sockets.h @@ -35,7 +35,7 @@ int inet_connect_saddr(InetSocketAddress *saddr, Error **errp); NetworkAddressFamily inet_netfamily(int family); -int unix_listen(const char *path, char *ostr, int olen, Error **errp); +int unix_listen(const char *path, Error **errp); int unix_connect(const char *path, Error **errp); SocketAddress *socket_parse(const char *str, Error **errp); diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 3dbc69b1e9..9bd7a834ba 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -36,6 +36,7 @@ typedef struct FWCfgIoState FWCfgIoState; typedef struct FWCfgMemState FWCfgMemState; typedef struct FWCfgState FWCfgState; typedef struct HCIInfo HCIInfo; +typedef struct HVFX86EmulatorState HVFX86EmulatorState; typedef struct I2CBus I2CBus; typedef struct I2SCodec I2SCodec; typedef struct ISABus ISABus; diff --git a/include/qemu/uuid.h b/include/qemu/uuid.h index afe4840296..09489ce5c5 100644 --- a/include/qemu/uuid.h +++ b/include/qemu/uuid.h @@ -48,6 +48,8 @@ void qemu_uuid_generate(QemuUUID *out); int qemu_uuid_is_null(const QemuUUID *uu); +int qemu_uuid_is_equal(const QemuUUID *lhv, const QemuUUID *rhv); + void qemu_uuid_unparse(const QemuUUID *uuid, char *out); char *qemu_uuid_unparse_strdup(const QemuUUID *uuid); diff --git a/include/qom/cpu.h b/include/qom/cpu.h index c2fa151228..93bd546879 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -423,6 +423,8 @@ struct CPUState { * unnecessary flushes. */ uint16_t pending_tlb_flush; + + int hvf_fd; }; QTAILQ_HEAD(CPUTailQ, CPUState); diff --git a/include/scsi/utils.h b/include/scsi/utils.h index 00a4bdb080..4b705f5e0f 100644 --- a/include/scsi/utils.h +++ b/include/scsi/utils.h @@ -31,6 +31,9 @@ typedef struct SCSISense { } SCSISense; int scsi_build_sense(uint8_t *buf, SCSISense sense); +SCSISense scsi_parse_sense_buf(const uint8_t *in_buf, int in_len); +int scsi_build_sense_buf(uint8_t *buf, size_t max_size, SCSISense sense, + bool fixed_sense); /* * Predefined sense codes @@ -76,7 +79,11 @@ extern const struct SCSISense sense_code_LUN_FAILURE; extern const struct SCSISense sense_code_LUN_COMM_FAILURE; /* Command aborted, Overlapped Commands Attempted */ extern const struct SCSISense sense_code_OVERLAPPED_COMMANDS; -/* LUN not ready, Capacity data has changed */ +/* Medium error, Unrecovered read error */ +extern const struct SCSISense sense_code_READ_ERROR; +/* LUN not ready, Cause not reportable */ +extern const struct SCSISense sense_code_NOT_READY; +/* Unit attention, Capacity data has changed */ extern const struct SCSISense sense_code_CAPACITY_CHANGED; /* Unit attention, SCSI bus reset */ extern const struct SCSISense sense_code_SCSI_BUS_RESET; diff --git a/include/standard-headers/asm-s390/virtio-ccw.h b/include/standard-headers/asm-s390/virtio-ccw.h index a9a4ebf79f..967aad3901 100644 --- a/include/standard-headers/asm-s390/virtio-ccw.h +++ b/include/standard-headers/asm-s390/virtio-ccw.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Definitions for virtio-ccw devices. * diff --git a/include/standard-headers/asm-x86/hyperv.h b/include/standard-headers/asm-x86/hyperv.h index 5f95d5ed02..ce87d0c344 100644 --- a/include/standard-headers/asm-x86/hyperv.h +++ b/include/standard-headers/asm-x86/hyperv.h @@ -1,393 +1 @@ -#ifndef _ASM_X86_HYPERV_H -#define _ASM_X86_HYPERV_H - -#include "standard-headers/linux/types.h" - -/* - * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent - * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). - */ -#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 -#define HYPERV_CPUID_INTERFACE 0x40000001 -#define HYPERV_CPUID_VERSION 0x40000002 -#define HYPERV_CPUID_FEATURES 0x40000003 -#define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 -#define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 - -#define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 -#define HYPERV_CPUID_MIN 0x40000005 -#define HYPERV_CPUID_MAX 0x4000ffff - -/* - * Feature identification. EAX indicates which features are available - * to the partition based upon the current partition privileges. - */ - -/* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */ -#define HV_X64_MSR_VP_RUNTIME_AVAILABLE (1 << 0) -/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/ -#define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1) -/* Partition reference TSC MSR is available */ -#define HV_X64_MSR_REFERENCE_TSC_AVAILABLE (1 << 9) - -/* A partition's reference time stamp counter (TSC) page */ -#define HV_X64_MSR_REFERENCE_TSC 0x40000021 - -/* - * There is a single feature flag that signifies if the partition has access - * to MSRs with local APIC and TSC frequencies. - */ -#define HV_X64_ACCESS_FREQUENCY_MSRS (1 << 11) - -/* - * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM - * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available - */ -#define HV_X64_MSR_SYNIC_AVAILABLE (1 << 2) -/* - * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through - * HV_X64_MSR_STIMER3_COUNT) available - */ -#define HV_X64_MSR_SYNTIMER_AVAILABLE (1 << 3) -/* - * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) - * are available - */ -#define HV_X64_MSR_APIC_ACCESS_AVAILABLE (1 << 4) -/* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/ -#define HV_X64_MSR_HYPERCALL_AVAILABLE (1 << 5) -/* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/ -#define HV_X64_MSR_VP_INDEX_AVAILABLE (1 << 6) -/* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/ -#define HV_X64_MSR_RESET_AVAILABLE (1 << 7) - /* - * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE, - * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE, - * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available - */ -#define HV_X64_MSR_STAT_PAGES_AVAILABLE (1 << 8) - -/* Frequency MSRs available */ -#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE (1 << 8) - -/* Crash MSR available */ -#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10) - -/* - * Feature identification: EBX indicates which flags were specified at - * partition creation. The format is the same as the partition creation - * flag structure defined in section Partition Creation Flags. - */ -#define HV_X64_CREATE_PARTITIONS (1 << 0) -#define HV_X64_ACCESS_PARTITION_ID (1 << 1) -#define HV_X64_ACCESS_MEMORY_POOL (1 << 2) -#define HV_X64_ADJUST_MESSAGE_BUFFERS (1 << 3) -#define HV_X64_POST_MESSAGES (1 << 4) -#define HV_X64_SIGNAL_EVENTS (1 << 5) -#define HV_X64_CREATE_PORT (1 << 6) -#define HV_X64_CONNECT_PORT (1 << 7) -#define HV_X64_ACCESS_STATS (1 << 8) -#define HV_X64_DEBUGGING (1 << 11) -#define HV_X64_CPU_POWER_MANAGEMENT (1 << 12) -#define HV_X64_CONFIGURE_PROFILER (1 << 13) - -/* - * Feature identification. EDX indicates which miscellaneous features - * are available to the partition. - */ -/* The MWAIT instruction is available (per section MONITOR / MWAIT) */ -#define HV_X64_MWAIT_AVAILABLE (1 << 0) -/* Guest debugging support is available */ -#define HV_X64_GUEST_DEBUGGING_AVAILABLE (1 << 1) -/* Performance Monitor support is available*/ -#define HV_X64_PERF_MONITOR_AVAILABLE (1 << 2) -/* Support for physical CPU dynamic partitioning events is available*/ -#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1 << 3) -/* - * Support for passing hypercall input parameter block via XMM - * registers is available - */ -#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE (1 << 4) -/* Support for a virtual guest idle state is available */ -#define HV_X64_GUEST_IDLE_STATE_AVAILABLE (1 << 5) -/* Guest crash data handler available */ -#define HV_X64_GUEST_CRASH_MSR_AVAILABLE (1 << 10) - -/* - * Implementation recommendations. Indicates which behaviors the hypervisor - * recommends the OS implement for optimal performance. - */ - /* - * Recommend using hypercall for address space switches rather - * than MOV to CR3 instruction - */ -#define HV_X64_AS_SWITCH_RECOMMENDED (1 << 0) -/* Recommend using hypercall for local TLB flushes rather - * than INVLPG or MOV to CR3 instructions */ -#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED (1 << 1) -/* - * Recommend using hypercall for remote TLB flushes rather - * than inter-processor interrupts - */ -#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED (1 << 2) -/* - * Recommend using MSRs for accessing APIC registers - * EOI, ICR and TPR rather than their memory-mapped counterparts - */ -#define HV_X64_APIC_ACCESS_RECOMMENDED (1 << 3) -/* Recommend using the hypervisor-provided MSR to initiate a system RESET */ -#define HV_X64_SYSTEM_RESET_RECOMMENDED (1 << 4) -/* - * Recommend using relaxed timing for this partition. If used, - * the VM should disable any watchdog timeouts that rely on the - * timely delivery of external interrupts - */ -#define HV_X64_RELAXED_TIMING_RECOMMENDED (1 << 5) - -/* - * Virtual APIC support - */ -#define HV_X64_DEPRECATING_AEOI_RECOMMENDED (1 << 9) - -/* Recommend using the newer ExProcessorMasks interface */ -#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED (1 << 11) - -/* - * Crash notification flag. - */ -#define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63) - -/* MSR used to identify the guest OS. */ -#define HV_X64_MSR_GUEST_OS_ID 0x40000000 - -/* MSR used to setup pages used to communicate with the hypervisor. */ -#define HV_X64_MSR_HYPERCALL 0x40000001 - -/* MSR used to provide vcpu index */ -#define HV_X64_MSR_VP_INDEX 0x40000002 - -/* MSR used to reset the guest OS. */ -#define HV_X64_MSR_RESET 0x40000003 - -/* MSR used to provide vcpu runtime in 100ns units */ -#define HV_X64_MSR_VP_RUNTIME 0x40000010 - -/* MSR used to read the per-partition time reference counter */ -#define HV_X64_MSR_TIME_REF_COUNT 0x40000020 - -/* MSR used to retrieve the TSC frequency */ -#define HV_X64_MSR_TSC_FREQUENCY 0x40000022 - -/* MSR used to retrieve the local APIC timer frequency */ -#define HV_X64_MSR_APIC_FREQUENCY 0x40000023 - -/* Define the virtual APIC registers */ -#define HV_X64_MSR_EOI 0x40000070 -#define HV_X64_MSR_ICR 0x40000071 -#define HV_X64_MSR_TPR 0x40000072 -#define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073 - -/* Define synthetic interrupt controller model specific registers. */ -#define HV_X64_MSR_SCONTROL 0x40000080 -#define HV_X64_MSR_SVERSION 0x40000081 -#define HV_X64_MSR_SIEFP 0x40000082 -#define HV_X64_MSR_SIMP 0x40000083 -#define HV_X64_MSR_EOM 0x40000084 -#define HV_X64_MSR_SINT0 0x40000090 -#define HV_X64_MSR_SINT1 0x40000091 -#define HV_X64_MSR_SINT2 0x40000092 -#define HV_X64_MSR_SINT3 0x40000093 -#define HV_X64_MSR_SINT4 0x40000094 -#define HV_X64_MSR_SINT5 0x40000095 -#define HV_X64_MSR_SINT6 0x40000096 -#define HV_X64_MSR_SINT7 0x40000097 -#define HV_X64_MSR_SINT8 0x40000098 -#define HV_X64_MSR_SINT9 0x40000099 -#define HV_X64_MSR_SINT10 0x4000009A -#define HV_X64_MSR_SINT11 0x4000009B -#define HV_X64_MSR_SINT12 0x4000009C -#define HV_X64_MSR_SINT13 0x4000009D -#define HV_X64_MSR_SINT14 0x4000009E -#define HV_X64_MSR_SINT15 0x4000009F - -/* - * Synthetic Timer MSRs. Four timers per vcpu. - */ -#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 -#define HV_X64_MSR_STIMER0_COUNT 0x400000B1 -#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 -#define HV_X64_MSR_STIMER1_COUNT 0x400000B3 -#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 -#define HV_X64_MSR_STIMER2_COUNT 0x400000B5 -#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 -#define HV_X64_MSR_STIMER3_COUNT 0x400000B7 - -/* Hyper-V guest crash notification MSR's */ -#define HV_X64_MSR_CRASH_P0 0x40000100 -#define HV_X64_MSR_CRASH_P1 0x40000101 -#define HV_X64_MSR_CRASH_P2 0x40000102 -#define HV_X64_MSR_CRASH_P3 0x40000103 -#define HV_X64_MSR_CRASH_P4 0x40000104 -#define HV_X64_MSR_CRASH_CTL 0x40000105 -#define HV_X64_MSR_CRASH_CTL_NOTIFY (1ULL << 63) -#define HV_X64_MSR_CRASH_PARAMS \ - (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) - -#define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 -#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 -#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ - (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) - -/* Declare the various hypercall operations. */ -#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002 -#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003 -#define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008 -#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013 -#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014 -#define HVCALL_POST_MESSAGE 0x005c -#define HVCALL_SIGNAL_EVENT 0x005d - -#define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE 0x00000001 -#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT 12 -#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK \ - (~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) - -#define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 -#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 - -#define HV_PROCESSOR_POWER_STATE_C0 0 -#define HV_PROCESSOR_POWER_STATE_C1 1 -#define HV_PROCESSOR_POWER_STATE_C2 2 -#define HV_PROCESSOR_POWER_STATE_C3 3 - -#define HV_FLUSH_ALL_PROCESSORS BIT(0) -#define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1) -#define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2) -#define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3) - -enum HV_GENERIC_SET_FORMAT { - HV_GENERIC_SET_SPARCE_4K, - HV_GENERIC_SET_ALL, -}; - -/* hypercall status code */ -#define HV_STATUS_SUCCESS 0 -#define HV_STATUS_INVALID_HYPERCALL_CODE 2 -#define HV_STATUS_INVALID_HYPERCALL_INPUT 3 -#define HV_STATUS_INVALID_ALIGNMENT 4 -#define HV_STATUS_INSUFFICIENT_MEMORY 11 -#define HV_STATUS_INVALID_CONNECTION_ID 18 -#define HV_STATUS_INSUFFICIENT_BUFFERS 19 - -typedef struct _HV_REFERENCE_TSC_PAGE { - uint32_t tsc_sequence; - uint32_t res1; - uint64_t tsc_scale; - int64_t tsc_offset; -} HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE; - -/* Define the number of synthetic interrupt sources. */ -#define HV_SYNIC_SINT_COUNT (16) -/* Define the expected SynIC version. */ -#define HV_SYNIC_VERSION_1 (0x1) - -#define HV_SYNIC_CONTROL_ENABLE (1ULL << 0) -#define HV_SYNIC_SIMP_ENABLE (1ULL << 0) -#define HV_SYNIC_SIEFP_ENABLE (1ULL << 0) -#define HV_SYNIC_SINT_MASKED (1ULL << 16) -#define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17) -#define HV_SYNIC_SINT_VECTOR_MASK (0xFF) - -#define HV_SYNIC_STIMER_COUNT (4) - -/* Define synthetic interrupt controller message constants. */ -#define HV_MESSAGE_SIZE (256) -#define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) -#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) - -/* Define hypervisor message types. */ -enum hv_message_type { - HVMSG_NONE = 0x00000000, - - /* Memory access messages. */ - HVMSG_UNMAPPED_GPA = 0x80000000, - HVMSG_GPA_INTERCEPT = 0x80000001, - - /* Timer notification messages. */ - HVMSG_TIMER_EXPIRED = 0x80000010, - - /* Error messages. */ - HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, - HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, - HVMSG_UNSUPPORTED_FEATURE = 0x80000022, - - /* Trace buffer complete messages. */ - HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, - - /* Platform-specific processor intercept messages. */ - HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, - HVMSG_X64_MSR_INTERCEPT = 0x80010001, - HVMSG_X64_CPUID_INTERCEPT = 0x80010002, - HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, - HVMSG_X64_APIC_EOI = 0x80010004, - HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 -}; - -/* Define synthetic interrupt controller message flags. */ -union hv_message_flags { - uint8_t asu8; - struct { - uint8_t msg_pending:1; - uint8_t reserved:7; - }; -}; - -/* Define port identifier type. */ -union hv_port_id { - uint32_t asu32; - struct { - uint32_t id:24; - uint32_t reserved:8; - } u; -}; - -/* Define synthetic interrupt controller message header. */ -struct hv_message_header { - uint32_t message_type; - uint8_t payload_size; - union hv_message_flags message_flags; - uint8_t reserved[2]; - union { - uint64_t sender; - union hv_port_id port; - }; -}; - -/* Define synthetic interrupt controller message format. */ -struct hv_message { - struct hv_message_header header; - union { - uint64_t payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; - } u; -}; - -/* Define the synthetic interrupt message page layout. */ -struct hv_message_page { - struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; -}; - -/* Define timer message payload structure. */ -struct hv_timer_message_payload { - uint32_t timer_index; - uint32_t reserved; - uint64_t expiration_time; /* When the timer expired */ - uint64_t delivery_time; /* When the message was delivered */ -}; - -#define HV_STIMER_ENABLE (1ULL << 0) -#define HV_STIMER_PERIODIC (1ULL << 1) -#define HV_STIMER_LAZY (1ULL << 2) -#define HV_STIMER_AUTOENABLE (1ULL << 3) -#define HV_STIMER_SINT(config) (uint8_t)(((config) >> 16) & 0x0F) - -#endif + /* this is a temporary placeholder until kvm_para.h stops including it */ diff --git a/include/standard-headers/linux/input-event-codes.h b/include/standard-headers/linux/input-event-codes.h index 2fa0f4ea6b..79841b543f 100644 --- a/include/standard-headers/linux/input-event-codes.h +++ b/include/standard-headers/linux/input-event-codes.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Input event codes * @@ -406,6 +407,7 @@ #define BTN_TOOL_MOUSE 0x146 #define BTN_TOOL_LENS 0x147 #define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ +#define BTN_STYLUS3 0x149 #define BTN_TOUCH 0x14a #define BTN_STYLUS 0x14b #define BTN_STYLUS2 0x14c diff --git a/include/standard-headers/linux/input.h b/include/standard-headers/linux/input.h index 666e201ddb..bc3e6d3d5b 100644 --- a/include/standard-headers/linux/input.h +++ b/include/standard-headers/linux/input.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Copyright (c) 1999-2002 Vojtech Pavlik * diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h index f8d5804592..70c2b2ade0 100644 --- a/include/standard-headers/linux/pci_regs.h +++ b/include/standard-headers/linux/pci_regs.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * pci_regs.h * @@ -746,6 +747,7 @@ #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */ #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ +#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ /* Virtual Channel */ @@ -939,9 +941,13 @@ #define PCI_SATA_SIZEOF_LONG 16 /* Resizable BARs */ +#define PCI_REBAR_CAP 4 /* capability register */ +#define PCI_REBAR_CAP_SIZES 0x00FFFFF0 /* supported BAR sizes */ #define PCI_REBAR_CTRL 8 /* control register */ -#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */ -#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */ +#define PCI_REBAR_CTRL_BAR_IDX 0x00000007 /* BAR index */ +#define PCI_REBAR_CTRL_NBAR_MASK 0x000000E0 /* # of resizable BARs */ +#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # of BARs */ +#define PCI_REBAR_CTRL_BAR_SIZE 0x00001F00 /* BAR size */ /* Dynamic Power Allocation */ #define PCI_DPA_CAP 4 /* capability register */ @@ -960,6 +966,7 @@ /* Downstream Port Containment */ #define PCI_EXP_DPC_CAP 4 /* DPC Capability */ +#define PCI_EXP_DPC_IRQ 0x1f /* DPC Interrupt Message Number */ #define PCI_EXP_DPC_CAP_RP_EXT 0x20 /* Root Port Extensions for DPC */ #define PCI_EXP_DPC_CAP_POISONED_TLP 0x40 /* Poisoned TLP Egress Blocking Supported */ #define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80 /* Software Triggering Supported */ @@ -995,19 +1002,25 @@ #define PCI_PTM_CTRL_ENABLE 0x00000001 /* PTM enable */ #define PCI_PTM_CTRL_ROOT 0x00000002 /* Root select */ -/* L1 PM Substates */ -#define PCI_L1SS_CAP 4 /* capability register */ -#define PCI_L1SS_CAP_PCIPM_L1_2 1 /* PCI PM L1.2 Support */ -#define PCI_L1SS_CAP_PCIPM_L1_1 2 /* PCI PM L1.1 Support */ -#define PCI_L1SS_CAP_ASPM_L1_2 4 /* ASPM L1.2 Support */ -#define PCI_L1SS_CAP_ASPM_L1_1 8 /* ASPM L1.1 Support */ -#define PCI_L1SS_CAP_L1_PM_SS 16 /* L1 PM Substates Support */ -#define PCI_L1SS_CTL1 8 /* Control Register 1 */ -#define PCI_L1SS_CTL1_PCIPM_L1_2 1 /* PCI PM L1.2 Enable */ -#define PCI_L1SS_CTL1_PCIPM_L1_1 2 /* PCI PM L1.1 Support */ -#define PCI_L1SS_CTL1_ASPM_L1_2 4 /* ASPM L1.2 Support */ -#define PCI_L1SS_CTL1_ASPM_L1_1 8 /* ASPM L1.1 Support */ -#define PCI_L1SS_CTL1_L1SS_MASK 0x0000000F -#define PCI_L1SS_CTL2 0xC /* Control Register 2 */ +/* ASPM L1 PM Substates */ +#define PCI_L1SS_CAP 0x04 /* Capabilities Register */ +#define PCI_L1SS_CAP_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Supported */ +#define PCI_L1SS_CAP_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Supported */ +#define PCI_L1SS_CAP_ASPM_L1_2 0x00000004 /* ASPM L1.2 Supported */ +#define PCI_L1SS_CAP_ASPM_L1_1 0x00000008 /* ASPM L1.1 Supported */ +#define PCI_L1SS_CAP_L1_PM_SS 0x00000010 /* L1 PM Substates Supported */ +#define PCI_L1SS_CAP_CM_RESTORE_TIME 0x0000ff00 /* Port Common_Mode_Restore_Time */ +#define PCI_L1SS_CAP_P_PWR_ON_SCALE 0x00030000 /* Port T_POWER_ON scale */ +#define PCI_L1SS_CAP_P_PWR_ON_VALUE 0x00f80000 /* Port T_POWER_ON value */ +#define PCI_L1SS_CTL1 0x08 /* Control 1 Register */ +#define PCI_L1SS_CTL1_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Enable */ +#define PCI_L1SS_CTL1_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Enable */ +#define PCI_L1SS_CTL1_ASPM_L1_2 0x00000004 /* ASPM L1.2 Enable */ +#define PCI_L1SS_CTL1_ASPM_L1_1 0x00000008 /* ASPM L1.1 Enable */ +#define PCI_L1SS_CTL1_L1SS_MASK 0x0000000f +#define PCI_L1SS_CTL1_CM_RESTORE_TIME 0x0000ff00 /* Common_Mode_Restore_Time */ +#define PCI_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 /* LTR_L1.2_THRESHOLD_Value */ +#define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ +#define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ #endif /* LINUX_PCI_REGS_H */ diff --git a/include/sysemu/hax.h b/include/sysemu/hax.h index 232a68ab1b..f252399623 100644 --- a/include/sysemu/hax.h +++ b/include/sysemu/hax.h @@ -22,7 +22,6 @@ #ifndef QEMU_HAX_H #define QEMU_HAX_H -#include "config-host.h" #include "qemu-common.h" int hax_sync_vcpus(void); diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h new file mode 100644 index 0000000000..e4e43f6468 --- /dev/null +++ b/include/sysemu/hvf.h @@ -0,0 +1,107 @@ +/* + * QEMU Hypervisor.framework (HVF) support + * + * Copyright Google Inc., 2017 + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +/* header to be included in non-HVF-specific code */ +#ifndef _HVF_H +#define _HVF_H + +#include "config-host.h" +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/bitops.h" +#include "exec/memory.h" +#include "sysemu/accel.h" + +extern int hvf_disabled; +#ifdef CONFIG_HVF +#include <Hypervisor/hv.h> +#include <Hypervisor/hv_vmx.h> +#include <Hypervisor/hv_error.h> +#include "target/i386/cpu.h" +#include "hw/hw.h" +uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx, + int reg); +#define hvf_enabled() !hvf_disabled +#else +#define hvf_enabled() 0 +#define hvf_get_supported_cpuid(func, idx, reg) 0 +#endif + +/* hvf_slot flags */ +#define HVF_SLOT_LOG (1 << 0) + +typedef struct hvf_slot { + uint64_t start; + uint64_t size; + uint8_t *mem; + int slot_id; + uint32_t flags; + MemoryRegion *region; +} hvf_slot; + +typedef struct hvf_vcpu_caps { + uint64_t vmx_cap_pinbased; + uint64_t vmx_cap_procbased; + uint64_t vmx_cap_procbased2; + uint64_t vmx_cap_entry; + uint64_t vmx_cap_exit; + uint64_t vmx_cap_preemption_timer; +} hvf_vcpu_caps; + +typedef struct HVFState { + AccelState parent; + hvf_slot slots[32]; + int num_slots; + + hvf_vcpu_caps *hvf_caps; +} HVFState; +extern HVFState *hvf_state; + +void hvf_set_phys_mem(MemoryRegionSection *, bool); +void hvf_handle_io(CPUArchState *, uint16_t, void *, + int, int, int); +hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t); + +/* Disable HVF if |disable| is 1, otherwise, enable it iff it is supported by + * the host CPU. Use hvf_enabled() after this to get the result. */ +void hvf_disable(int disable); + +/* Returns non-0 if the host CPU supports the VMX "unrestricted guest" feature + * which allows the virtual CPU to directly run in "real mode". If true, this + * allows QEMU to run several vCPU threads in parallel (see cpus.c). Otherwise, + * only a a single TCG thread can run, and it will call HVF to run the current + * instructions, except in case of "real mode" (paging disabled, typically at + * boot time), or MMIO operations. */ + +int hvf_sync_vcpus(void); + +int hvf_init_vcpu(CPUState *); +int hvf_vcpu_exec(CPUState *); +int hvf_smp_cpu_exec(CPUState *); +void hvf_cpu_synchronize_state(CPUState *); +void hvf_cpu_synchronize_post_reset(CPUState *); +void hvf_cpu_synchronize_post_init(CPUState *); +void _hvf_cpu_synchronize_post_init(CPUState *, run_on_cpu_data); + +void hvf_vcpu_destroy(CPUState *); +void hvf_raise_event(CPUState *); +/* void hvf_reset_vcpu_state(void *opaque); */ +void hvf_reset_vcpu(CPUState *); +void vmx_update_tpr(CPUState *); +void update_apic_tpr(CPUState *); +int hvf_put_registers(CPUState *); +void vmx_clear_int_window_exiting(CPUState *cpu); + +#define TYPE_HVF_ACCEL ACCEL_CLASS_NAME("hvf") + +#define HVF_STATE(obj) \ + OBJECT_CHECK(HVFState, (obj), TYPE_HVF_ACCEL) + +#endif diff --git a/include/sysemu/iothread.h b/include/sysemu/iothread.h index 110329b2b4..799614ffd2 100644 --- a/include/sysemu/iothread.h +++ b/include/sysemu/iothread.h @@ -29,7 +29,8 @@ typedef struct { GOnce once; QemuMutex init_done_lock; QemuCond init_done_cond; /* is thread initialization done? */ - bool stopping; + bool stopping; /* has iothread_stop() been called? */ + bool running; /* should iothread_run() continue? */ int thread_id; /* AioContext poll parameters */ @@ -42,6 +43,7 @@ typedef struct { OBJECT_CHECK(IOThread, obj, TYPE_IOTHREAD) char *iothread_get_id(IOThread *iothread); +IOThread *iothread_by_id(const char *id); AioContext *iothread_get_aio_context(IOThread *iothread); void iothread_stop_all(void); GMainContext *iothread_get_g_main_context(IOThread *iothread); diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h index 5c6df2820b..b3545215f6 100644 --- a/include/sysemu/numa.h +++ b/include/sysemu/numa.h @@ -10,17 +10,10 @@ extern int nb_numa_nodes; /* Number of NUMA nodes */ extern bool have_numa_distance; -struct numa_addr_range { - ram_addr_t mem_start; - ram_addr_t mem_end; - QLIST_ENTRY(numa_addr_range) entry; -}; - struct node_info { uint64_t node_mem; struct HostMemoryBackend *node_memdev; bool present; - QLIST_HEAD(, numa_addr_range) addr; /* List to store address ranges */ uint8_t distance[MAX_NODES]; }; @@ -33,9 +26,6 @@ extern NodeInfo numa_info[MAX_NODES]; void parse_numa_opts(MachineState *ms); void query_numa_node_mem(NumaNodeMem node_mem[]); extern QemuOptsList qemu_numa_opts; -void numa_set_mem_node_id(ram_addr_t addr, uint64_t size, uint32_t node); -void numa_unset_mem_node_id(ram_addr_t addr, uint64_t size, uint32_t node); -uint32_t numa_get_node(ram_addr_t addr, Error **errp); void numa_legacy_auto_assign_ram(MachineClass *mc, NodeInfo *nodes, int nb_nodes, ram_addr_t size); void numa_default_auto_assign_ram(MachineClass *mc, NodeInfo *nodes, diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h index c083869fcf..31612caf10 100644 --- a/include/sysemu/sysemu.h +++ b/include/sysemu/sysemu.h @@ -166,8 +166,6 @@ extern Chardev *serial_hds[MAX_SERIAL_PORTS]; extern Chardev *parallel_hds[MAX_PARALLEL_PORTS]; -void hmp_usb_add(Monitor *mon, const QDict *qdict); -void hmp_usb_del(Monitor *mon, const QDict *qdict); void hmp_info_usb(Monitor *mon, const QDict *qdict); void add_boot_device_path(int32_t bootindex, DeviceState *dev, diff --git a/include/sysemu/tpm.h b/include/sysemu/tpm.h index d7a2bd8556..852e02687c 100644 --- a/include/sysemu/tpm.h +++ b/include/sysemu/tpm.h @@ -12,35 +12,59 @@ #ifndef QEMU_TPM_H #define QEMU_TPM_H -#include "qemu/option.h" #include "qom/object.h" - -typedef struct TPMState TPMState; +#include "qapi-types.h" int tpm_config_parse(QemuOptsList *opts_list, const char *optarg); int tpm_init(void); void tpm_cleanup(void); -typedef enum TPMVersion { +typedef enum TPMVersion { TPM_VERSION_UNSPEC = 0, TPM_VERSION_1_2 = 1, TPM_VERSION_2_0 = 2, } TPMVersion; -TPMVersion tpm_tis_get_tpm_version(Object *obj); +#define TYPE_TPM_IF "tpm-if" +#define TPM_IF_CLASS(klass) \ + OBJECT_CLASS_CHECK(TPMIfClass, (klass), TYPE_TPM_IF) +#define TPM_IF_GET_CLASS(obj) \ + OBJECT_GET_CLASS(TPMIfClass, (obj), TYPE_TPM_IF) +#define TPM_IF(obj) \ + INTERFACE_CHECK(TPMIf, (obj), TYPE_TPM_IF) + +typedef struct TPMIf { + Object parent_obj; +} TPMIf; + +typedef struct TPMIfClass { + InterfaceClass parent_class; + + enum TpmModel model; + void (*request_completed)(TPMIf *obj); + enum TPMVersion (*get_version)(TPMIf *obj); +} TPMIfClass; #define TYPE_TPM_TIS "tpm-tis" -static inline TPMVersion tpm_get_version(void) +#define TPM_IS_TIS(chr) \ + object_dynamic_cast(OBJECT(chr), TYPE_TPM_TIS) + +/* returns NULL unless there is exactly one TPM device */ +static inline TPMIf *tpm_find(void) { -#ifdef CONFIG_TPM - Object *obj = object_resolve_path_type("", TYPE_TPM_TIS, NULL); + Object *obj = object_resolve_path_type("", TYPE_TPM_IF, NULL); - if (obj) { - return tpm_tis_get_tpm_version(obj); + return TPM_IF(obj); +} + +static inline TPMVersion tpm_get_version(TPMIf *ti) +{ + if (!ti) { + return TPM_VERSION_UNSPEC; } -#endif - return TPM_VERSION_UNSPEC; + + return TPM_IF_GET_CLASS(ti)->get_version(ti); } #endif /* QEMU_TPM_H */ diff --git a/include/sysemu/tpm_backend.h b/include/sysemu/tpm_backend.h index 03ea5a3400..0d6c994a62 100644 --- a/include/sysemu/tpm_backend.h +++ b/include/sysemu/tpm_backend.h @@ -43,14 +43,14 @@ struct TPMBackend { Object parent; /*< protected >*/ + TPMIf *tpmif; bool opened; - TPMState *tpm_state; GThreadPool *thread_pool; bool had_startup_error; + QEMUBH *bh; /* <public> */ char *id; - enum TpmModel fe_model; QLIST_ENTRY(TPMBackend) list; }; @@ -63,24 +63,27 @@ struct TPMBackendClass { /* get a descriptive text of the backend to display to the user */ const char *desc; - TPMBackend *(*create)(QemuOpts *opts, const char *id); + TPMBackend *(*create)(QemuOpts *opts); - /* start up the TPM on the backend */ - int (*startup_tpm)(TPMBackend *t); + /* start up the TPM on the backend - optional */ + int (*startup_tpm)(TPMBackend *t, size_t buffersize); + /* optional */ void (*reset)(TPMBackend *t); void (*cancel_cmd)(TPMBackend *t); + /* optional */ bool (*get_tpm_established_flag)(TPMBackend *t); + /* optional */ int (*reset_tpm_established_flag)(TPMBackend *t, uint8_t locty); TPMVersion (*get_tpm_version)(TPMBackend *t); - TpmTypeOptions *(*get_tpm_options)(TPMBackend *t); + size_t (*get_buffer_size)(TPMBackend *t); - void (*opened)(TPMBackend *s, Error **errp); + TpmTypeOptions *(*get_tpm_options)(TPMBackend *t); void (*handle_request)(TPMBackend *s, TPMBackendCmd *cmd); }; @@ -96,22 +99,25 @@ enum TpmType tpm_backend_get_type(TPMBackend *s); /** * tpm_backend_init: * @s: the backend to initialized - * @state: TPMState + * @tpmif: TPM interface * @datacb: callback for sending data to frontend + * @errp: a pointer to return the #Error object if an error occurs. * * Initialize the backend with the given variables. * * Returns 0 on success. */ -int tpm_backend_init(TPMBackend *s, TPMState *state); +int tpm_backend_init(TPMBackend *s, TPMIf *tpmif, Error **errp); /** * tpm_backend_startup_tpm: * @s: the backend whose TPM support is to be started + * @buffersize: the buffer size the TPM is supposed to use, + * 0 to leave it as-is * * Returns 0 on success. */ -int tpm_backend_startup_tpm(TPMBackend *s); +int tpm_backend_startup_tpm(TPMBackend *s, size_t buffersize); /** * tpm_backend_had_startup_error: @@ -171,16 +177,6 @@ bool tpm_backend_get_tpm_established_flag(TPMBackend *s); int tpm_backend_reset_tpm_established_flag(TPMBackend *s, uint8_t locty); /** - * tpm_backend_open: - * @s: the backend to open - * @errp: a pointer to return the #Error object if an error occurs. - * - * This function will open the backend if it is not already open. Calling this - * function on an already opened backend will not result in an error. - */ -void tpm_backend_open(TPMBackend *s, Error **errp); - -/** * tpm_backend_get_tpm_version: * @s: the backend to call into * @@ -191,6 +187,16 @@ void tpm_backend_open(TPMBackend *s, Error **errp); TPMVersion tpm_backend_get_tpm_version(TPMBackend *s); /** + * tpm_backend_get_buffer_size: + * @s: the backend to call into + * + * Get the TPM's buffer size. + * + * Returns buffer size. + */ +size_t tpm_backend_get_buffer_size(TPMBackend *s); + +/** * tpm_backend_query_tpm: * @s: the backend * @@ -200,8 +206,6 @@ TPMVersion tpm_backend_get_tpm_version(TPMBackend *s); */ TPMInfo *tpm_backend_query_tpm(TPMBackend *s); -TPMBackend *qemu_find_tpm(const char *id); - -void tpm_register_model(enum TpmModel model); +TPMBackend *qemu_find_tpm_be(const char *id); #endif diff --git a/include/ui/input.h b/include/ui/input.h index f8cee43f65..5cc76d6e41 100644 --- a/include/ui/input.h +++ b/include/ui/input.h @@ -77,4 +77,7 @@ extern const guint16 qemu_input_map_qcode_to_qnum[]; extern const guint qemu_input_map_qnum_to_qcode_len; extern const guint16 qemu_input_map_qnum_to_qcode[]; +extern const guint qemu_input_map_qcode_to_linux_len; +extern const guint16 qemu_input_map_qcode_to_linux[]; + #endif /* INPUT_H */ |