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authorCédric Le Goater <clg@kaod.org>2018-08-16 14:05:29 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-08-16 14:29:58 +0100
commitebe31c0a8ef7b59fd96171fe694339ce69ee24a6 (patch)
tree374a67f4d65ac04241b9d52e1cec78089dc5503c /include
parenta7b4569a4dddf0255d29ec56045c65f9bcb60919 (diff)
aspeed: add a max_ram_size property to the memory controller
This will be used to construct a memory region beyond the RAM region to let firmwares scan the address space with load/store to guess how much RAM the SoC has. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180807075757.7242-7-joel@jms.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include')
-rw-r--r--include/hw/misc/aspeed_sdmc.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h
index e079c66a7d..b3c926acae 100644
--- a/include/hw/misc/aspeed_sdmc.h
+++ b/include/hw/misc/aspeed_sdmc.h
@@ -27,6 +27,7 @@ typedef struct AspeedSDMCState {
uint32_t silicon_rev;
uint32_t ram_bits;
uint64_t ram_size;
+ uint64_t max_ram_size;
uint32_t fixed_conf;
} AspeedSDMCState;