diff options
| author | Alistair Francis <Alistair.Francis@wdc.com> | 2019-04-20 02:24:09 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-05-24 12:09:23 -0700 |
| commit | 8903bf6e6d73d03b988b4a8197132de2ad681ff5 (patch) | |
| tree | f8f46e29bf4bc73a54fa9b63050c98bbe32dab31 /include | |
| parent | c4e95030ba3532d13aa4e6f0738326f6f2d0c2bf (diff) | |
target/riscv: Add a base 32 and 64 bit CPU
At the same time deprecate the ISA string CPUs.
It is dobtful anyone specifies the CPUs, but we are keeping them for the
Spike machine (which is about to be depreated) so we may as well just
mark them as deprecated.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/riscv/virt.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 568764b570..d01a1a85c4 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -74,9 +74,9 @@ enum { FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS) #if defined(TARGET_RISCV32) -#define VIRT_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 +#define VIRT_CPU TYPE_RISCV_CPU_BASE32 #elif defined(TARGET_RISCV64) -#define VIRT_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0 +#define VIRT_CPU TYPE_RISCV_CPU_BASE64 #endif #endif |