diff options
author | Cédric Le Goater <clg@kaod.org> | 2019-03-07 23:35:34 +0100 |
---|---|---|
committer | David Gibson <david@gibson.dropbear.id.au> | 2019-03-12 14:33:04 +1100 |
commit | ae85605531cde2856d0b37804dc9a32028d89a34 (patch) | |
tree | 264745ccbb72580e9e271ba6185aa83206ee0c19 /include | |
parent | 31bc6fa7fa8124ff8fb08373f9402985c806919f (diff) |
ppc/pnv: add a PSI bridge class model
To ease the introduction of the PSI bridge model for POWER9, abstract
the POWER chip differences in a PnvPsi class model and introduce a
specific Pnv8Psi type for POWER8. POWER8 interface to the interrupt
controller is still XICS whereas POWER9 uses the new XIVE model.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190307223548.20516-2-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include')
-rw-r--r-- | include/hw/ppc/pnv.h | 2 | ||||
-rw-r--r-- | include/hw/ppc/pnv_psi.h | 29 |
2 files changed, 28 insertions, 3 deletions
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index eb4bba25b3..3b5f9cd531 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -71,7 +71,7 @@ typedef struct Pnv8Chip { MemoryRegion icp_mmio; PnvLpcController lpc; - PnvPsi psi; + Pnv8Psi psi; PnvOCC occ; } Pnv8Chip; diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h index 64ac73512e..7087cbcb9a 100644 --- a/include/hw/ppc/pnv_psi.h +++ b/include/hw/ppc/pnv_psi.h @@ -39,7 +39,6 @@ typedef struct PnvPsi { uint64_t fsp_bar; /* Interrupt generation */ - ICSState ics; qemu_irq *qirqs; /* Registers */ @@ -48,6 +47,32 @@ typedef struct PnvPsi { MemoryRegion xscom_regs; } PnvPsi; +#define TYPE_PNV8_PSI TYPE_PNV_PSI "-POWER8" +#define PNV8_PSI(obj) \ + OBJECT_CHECK(Pnv8Psi, (obj), TYPE_PNV8_PSI) + +typedef struct Pnv8Psi { + PnvPsi parent; + + ICSState ics; +} Pnv8Psi; + +#define PNV_PSI_CLASS(klass) \ + OBJECT_CLASS_CHECK(PnvPsiClass, (klass), TYPE_PNV_PSI) +#define PNV_PSI_GET_CLASS(obj) \ + OBJECT_GET_CLASS(PnvPsiClass, (obj), TYPE_PNV_PSI) + +typedef struct PnvPsiClass { + SysBusDeviceClass parent_class; + + int chip_type; + uint32_t xscom_pcba; + uint32_t xscom_size; + uint64_t bar_mask; + + void (*irq_set)(PnvPsi *psi, int, bool state); +} PnvPsiClass; + /* The PSI and FSP interrupts are muxed on the same IRQ number */ typedef enum PnvPsiIrq { PSIHB_IRQ_PSI, /* internal use only */ @@ -61,6 +86,6 @@ typedef enum PnvPsiIrq { #define PSI_NUM_INTERRUPTS 6 -extern void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state); +void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state); #endif /* _PPC_PNV_PSI_H */ |