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authorMichael Clark <mjc@sifive.com>2018-03-03 01:31:09 +1300
committerMichael Clark <mjc@sifive.com>2018-03-07 08:30:28 +1300
commitf71a8eaffba3271cf7cdad95572f6996f7523a5b (patch)
treeff1c89e03772ce3a06fe9f4391245bfc66c9aef0 /include
parent4dc62b15323bb6338c4b426f76e92be55f87db8c (diff)
RISC-V ELF Machine Definition
Define RISC-V ELF machine EM_RISCV 243 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
Diffstat (limited to 'include')
-rw-r--r--include/elf.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/elf.h b/include/elf.h
index 943ee21171..c0dc9bb5fd 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -119,6 +119,8 @@ typedef int64_t Elf64_Sxword;
#define EM_UNICORE32 110 /* UniCore32 */
+#define EM_RISCV 243 /* RISC-V */
+
/*
* This is an interim value that we will use until the committee comes
* up with a final number.