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authorBin Meng <bin.meng@windriver.com>2020-07-02 20:21:51 -0700
committerAlistair Francis <alistair.francis@wdc.com>2020-07-13 17:25:37 -0700
commit2c44bbf32cda5fbf85b697e3a12127f59d2c2e80 (patch)
tree6f750f26ac604faf2a8f1938d52848b7a817cc8d /include
parente92fb01639cadbeb9c6fc5d5189e35ef3e45836f (diff)
hw/riscv: virt: Sort the SoC memmap table entries
Adjust the PCIe memory maps to follow the order. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1593746511-19517-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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