diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2021-11-16 09:56:28 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-11-16 09:56:28 +0100 |
| commit | 3e595538b8338ea7789d1d4003b0504258b6aa31 (patch) | |
| tree | d1b967ca12d9740b783483850cfefab32c8de579 /include | |
| parent | 757b8dd4e970038538b2e027120ab4594bebdebc (diff) | |
| parent | 1adf528ec3bdf62ea3b580b7ad562534a3676ff5 (diff) | |
Merge tag 'pull-target-arm-20211115-1' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Support multiple redistributor regions for TCG GICv3
* Send RTC_CHANGE QMP event from pl031
# gpg: Signature made Mon 15 Nov 2021 07:53:40 PM CET
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
* tag 'pull-target-arm-20211115-1' of https://git.linaro.org/people/pmaydell/qemu-arm:
hw/rtc/pl031: Send RTC_CHANGE QMP event
hw/intc/arm_gicv3: Support multiple redistributor regions
hw/intc/arm_gicv3: Set GICR_TYPER.Last correctly when nb_redist_regions > 1
hw/intc/arm_gicv3: Move checking of redist-region-count to arm_gicv3_common_realize
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/intc/arm_gicv3_common.h | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index aa4f0d6770..fc38e4b7dc 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -215,13 +215,23 @@ struct GICv3CPUState { bool seenbetter; }; +/* + * The redistributor pages might be split into more than one region + * on some machine types if there are many CPUs. + */ +typedef struct GICv3RedistRegion { + GICv3State *gic; + MemoryRegion iomem; + uint32_t cpuidx; /* index of first CPU this region covers */ +} GICv3RedistRegion; + struct GICv3State { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ MemoryRegion iomem_dist; /* Distributor */ - MemoryRegion *iomem_redist; /* Redistributor Regions */ + GICv3RedistRegion *redist_regions; /* Redistributor Regions */ uint32_t *redist_region_count; /* redistributor count within each region */ uint32_t nb_redist_regions; /* number of redist regions */ @@ -306,6 +316,6 @@ struct ARMGICv3CommonClass { }; void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, - const MemoryRegionOps *ops, Error **errp); + const MemoryRegionOps *ops); #endif |