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authorBharata B Rao <bharata@linux.ibm.com>2019-12-19 08:44:44 +0530
committerDavid Gibson <david@gibson.dropbear.id.au>2020-01-08 11:01:59 +1100
commit50fd0c375bef09d22b6828972c4ed4f945c95ed8 (patch)
tree5962be76fdcafe78633b7420d2b2a1b823182b63 /include/standard-headers/linux/pci_regs.h
parentbc5fdfc0a1377418902e215f8d7be00e46b9ac9c (diff)
linux-headers: Update
Update to mainline commit: d1eef1c61974 ("Linux 5.5-rc2") Signed-off-by: Bharata B Rao <bharata@linux.ibm.com> Message-Id: <20191219031445.8949-2-bharata@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include/standard-headers/linux/pci_regs.h')
-rw-r--r--include/standard-headers/linux/pci_regs.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h
index 29d6e93fd1..acb7d2bdb4 100644
--- a/include/standard-headers/linux/pci_regs.h
+++ b/include/standard-headers/linux/pci_regs.h
@@ -34,6 +34,7 @@
* of which the first 64 bytes are standardized as follows:
*/
#define PCI_STD_HEADER_SIZEOF 64
+#define PCI_STD_NUM_BARS 6 /* Number of standard BARs */
#define PCI_VENDOR_ID 0x00 /* 16 bits */
#define PCI_DEVICE_ID 0x02 /* 16 bits */
#define PCI_COMMAND 0x04 /* 16 bits */
@@ -673,6 +674,8 @@
#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
+#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
+#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */