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authorPeter Maydell <peter.maydell@linaro.org>2019-06-10 16:09:19 +0100
committerPeter Maydell <peter.maydell@linaro.org>2019-06-10 16:09:19 +0100
commita578cdfbdd8f9beff5ced52b7826ddb1669abbbf (patch)
tree90697278e6aefd0b91858c403ddb5670f6bdf053 /include/qom
parent19735c837ae2056b4651720290eda59498eca65a (diff)
parent43b3952dea0f763ceeaa2f119c473b5cc6d29c90 (diff)
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190610' into staging
Move softmmu tlb into CPUNegativeOffsetState # gpg: Signature made Mon 10 Jun 2019 15:07:55 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20190610: (39 commits) tcg/arm: Remove mostly unreachable tlb special case tcg/arm: Use LDRD to load tlb mask+table tcg/aarch64: Use LDP to load tlb mask+table cpu: Remove CPU_COMMON cpu: Move the softmmu tlb to CPUNegativeOffsetState cpu: Move icount_decr to CPUNegativeOffsetState cpu: Introduce CPUNegativeOffsetState cpu: Introduce cpu_set_cpustate_pointers cpu: Move ENV_OFFSET to exec/gen-icount.h target/xtensa: Use env_cpu, env_archcpu target/unicore32: Use env_cpu, env_archcpu target/tricore: Use env_cpu target/tilegx: Use env_cpu target/sparc: Use env_cpu, env_archcpu target/sh4: Use env_cpu, env_archcpu target/s390x: Use env_cpu, env_archcpu target/riscv: Use env_cpu, env_archcpu target/ppc: Use env_cpu, env_archcpu target/openrisc: Use env_cpu, env_archcpu target/nios2: Use env_cpu, env_archcpu ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/qom')
-rw-r--r--include/qom/cpu.h40
1 files changed, 18 insertions, 22 deletions
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 98e12d914c..5ee0046b62 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -232,17 +232,25 @@ typedef struct CPUClass {
bool gdb_stop_before_watchpoint;
} CPUClass;
+/*
+ * Low 16 bits: number of cycles left, used only in icount mode.
+ * High 16 bits: Set to -1 to force TCG to stop executing linked TBs
+ * for this CPU and return to its top level loop (even in non-icount mode).
+ * This allows a single read-compare-cbranch-write sequence to test
+ * for both decrementer underflow and exceptions.
+ */
+typedef union IcountDecr {
+ uint32_t u32;
+ struct {
#ifdef HOST_WORDS_BIGENDIAN
-typedef struct icount_decr_u16 {
- uint16_t high;
- uint16_t low;
-} icount_decr_u16;
+ uint16_t high;
+ uint16_t low;
#else
-typedef struct icount_decr_u16 {
- uint16_t low;
- uint16_t high;
-} icount_decr_u16;
+ uint16_t low;
+ uint16_t high;
#endif
+ } u16;
+} IcountDecr;
typedef struct CPUBreakpoint {
vaddr pc;
@@ -314,11 +322,6 @@ struct qemu_work_item;
* @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
* @singlestep_enabled: Flags for single-stepping.
* @icount_extra: Instructions until next timer event.
- * @icount_decr: Low 16 bits: number of cycles left, only used in icount mode.
- * High 16 bits: Set to -1 to force TCG to stop executing linked TBs for this
- * CPU and return to its top level loop (even in non-icount mode).
- * This allows a single read-compare-cbranch-write sequence to test
- * for both decrementer underflow and exceptions.
* @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution
* requires that IO only be performed on the last instruction of a TB
* so that interrupts take effect immediately.
@@ -328,6 +331,7 @@ struct qemu_work_item;
* @as: Pointer to the first AddressSpace, for the convenience of targets which
* only have a single AddressSpace
* @env_ptr: Pointer to subclass-specific CPUArchState field.
+ * @icount_decr_ptr: Pointer to IcountDecr field within subclass.
* @gdb_regs: Additional GDB registers.
* @gdb_num_regs: Number of total registers accessible to GDB.
* @gdb_num_g_regs: Number of registers in GDB 'g' packets.
@@ -387,6 +391,7 @@ struct CPUState {
MemoryRegion *memory;
void *env_ptr; /* CPUArchState */
+ IcountDecr *icount_decr_ptr;
/* Accessed in parallel; all accesses must be atomic */
struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
@@ -441,15 +446,6 @@ struct CPUState {
bool ignore_memory_transaction_failures;
- /* Note that this is accessed at the start of every TB via a negative
- offset from AREG0. Leave this field at the end so as to make the
- (absolute value) offset as small as possible. This reduces code
- size, especially for hosts without large memory offsets. */
- union {
- uint32_t u32;
- icount_decr_u16 u16;
- } icount_decr;
-
struct hax_vcpu_state *hax_vcpu;
int hvf_fd;