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authorManos Pitsidianakis <manos.pitsidianakis@linaro.org>2024-02-20 10:52:18 +0200
committerMichael Tokarev <mjt@tls.msk.ru>2024-02-21 08:16:43 +0300
commitc3df8c3084644d327b5007ff92e479d38b9a3050 (patch)
tree463c3273c47d02bcc0d3fc9c9c36dfec3c3ed5b8 /include/hw
parentc3aa4206fc5b5243632d58b8b8680ea068cf79ae (diff)
hw/cxl/cxl_device.h: correct typos
Correct typos automatically found with the `typos` tool <https://crates.io/crates/typos> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'include/hw')
-rw-r--r--include/hw/cxl/cxl_device.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index d8e184c4ba..279b276bda 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -268,7 +268,7 @@ void cxl_event_set_status(CXLDeviceState *cxl_dstate, CXLEventLogType log_type,
/*
* Helper macro to initialize capability headers for CXL devices.
*
- * In CXL r3.1 Section 8.2.8.2: CXL Device Capablity Header Register, this is
+ * In CXL r3.1 Section 8.2.8.2: CXL Device Capability Header Register, this is
* listed as a 128b register, but in CXL r3.1 Section 8.2.8: CXL Device Register
* Interface, it says:
* > No registers defined in Section 8.2.8 are larger than 64-bits wide so that
@@ -276,7 +276,7 @@ void cxl_event_set_status(CXLDeviceState *cxl_dstate, CXLEventLogType log_type,
* > followed, the behavior is undefined.
*
* > To illustrate how the fields fit together, the layouts ... are shown as
- * > wider than a 64 bit register. Implemenations are expected to use any size
+ * > wider than a 64 bit register. Implementations are expected to use any size
* > accesses for this information up to 64 bits without lost of functionality
*
* Here we've chosen to make it 4 dwords.