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authorRichard Henderson <richard.henderson@linaro.org>2023-09-12 17:47:56 -0700
committerRichard Henderson <richard.henderson@linaro.org>2023-10-03 08:01:02 -0700
commit3b3d7df545ff30762b169147398dbf90c42eb452 (patch)
treec387d03683d0643e6975c3387beda3c5ed8d9fd5 /include/hw
parent5d30bdcb1b72ec1d44397ee7047417617066d97a (diff)
accel/tcg: Move CPUNegativeOffsetState into CPUState
Retain the separate structure to emphasize its importance. Enforce CPUArchState always follows CPUState without padding. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include/hw')
-rw-r--r--include/hw/core/cpu.h17
1 files changed, 15 insertions, 2 deletions
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 04baa5063c..115ddf6d8a 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -345,8 +345,8 @@ typedef union IcountDecr {
} IcountDecr;
/*
- * This structure must be placed in ArchCPU immediately
- * before CPUArchState, as a field named "neg".
+ * Elements of CPUState most efficiently accessed from CPUArchState,
+ * via small negative offsets.
*/
typedef struct CPUNegativeOffsetState {
CPUTLB tlb;
@@ -453,6 +453,9 @@ struct qemu_work_item;
* dirty ring structure.
*
* State of one CPU core or thread.
+ *
+ * Align, in order to match possible alignment required by CPUArchState,
+ * and eliminate a hole between CPUState and CPUArchState within ArchCPU.
*/
struct CPUState {
/*< private >*/
@@ -571,8 +574,18 @@ struct CPUState {
/* track IOMMUs whose translations we've cached in the TCG TLB */
GArray *iommu_notifiers;
+
+ /*
+ * MUST BE LAST in order to minimize the displacement to CPUArchState.
+ */
+ char neg_align[-sizeof(CPUNegativeOffsetState) % 16] QEMU_ALIGNED(16);
+ CPUNegativeOffsetState neg;
};
+/* Validate placement of CPUNegativeOffsetState. */
+QEMU_BUILD_BUG_ON(offsetof(CPUState, neg) !=
+ sizeof(CPUState) - sizeof(CPUNegativeOffsetState));
+
typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ;
extern CPUTailQ cpus;