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authorBernhard Beschow <shentey@gmail.com>2023-02-13 18:30:28 +0100
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2023-02-27 22:29:01 +0100
commit20fe3af24f1367906ab1eb6aa56e2cef73f116a8 (patch)
tree4fe06f3747a20144bf125204aaeb3b0af82e8347 /include/hw
parentecf403cbb87020c6215856cb4843ca49c0202ba2 (diff)
hw/isa/lpc_ich9: Connect PM stuff to LPC internally
Make TYPE_ICH9_LPC_DEVICE more self-contained by moving the call to ich9_lpc_pm_init() from board code to its realize function. In order to propagate x86_machine_is_smm_enabled(), introduce an "smm-enabled" property like we have in piix4. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230213173033.98762-8-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'include/hw')
-rw-r--r--include/hw/acpi/ich9.h6
-rw-r--r--include/hw/i386/ich9.h2
2 files changed, 2 insertions, 6 deletions
diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h
index d41866a229..57a542c4b8 100644
--- a/include/hw/acpi/ich9.h
+++ b/include/hw/acpi/ich9.h
@@ -64,7 +64,7 @@ typedef struct ICH9LPCPMRegs {
uint8_t disable_s3;
uint8_t disable_s4;
uint8_t s4_val;
- uint8_t smm_enabled;
+ bool smm_enabled;
bool smm_compat;
bool enable_tco;
TCOIORegs tco_regs;
@@ -72,9 +72,7 @@ typedef struct ICH9LPCPMRegs {
#define ACPI_PM_PROP_TCO_ENABLED "enable_tco"
-void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
- bool smm_enabled,
- qemu_irq sci_irq);
+void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, qemu_irq sci_irq);
void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
extern const VMStateDescription vmstate_ich9_pm;
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index 52ea116f44..433c8942c9 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -8,8 +8,6 @@
#include "hw/acpi/ich9.h"
#include "qom/object.h"
-void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
-
void ich9_generate_smi(void);
#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */