diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2020-12-10 12:53:01 +0000 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2020-12-10 12:53:01 +0000 |
commit | 00ef48ff0de9c3e5834e7e3f6691bbc80d08c114 (patch) | |
tree | a7951d85541644a945f1a9337465c4b3102da902 /include/hw | |
parent | 180834dcb8277a687b62f035b477abfd5a1ff978 (diff) | |
parent | 08af4e13f8d4db099bc444f83879c32459df7f3a (diff) |
Merge remote-tracking branch 'remotes/kraxel/tags/microvm-20201210-pull-request' into staging
microvm: add support for second ioapic
# gpg: Signature made Thu 10 Dec 2020 12:13:42 GMT
# gpg: using RSA key 4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* remotes/kraxel/tags/microvm-20201210-pull-request:
tests/acpi: disallow updates for expected data files
tests/acpi: update expected data files
tests/acpi: add ioapic2=on test for microvm
tests/acpi: add data files for ioapic2 test variant
tests/acpi: allow updates for expected data files
microvm: add second ioapic
microvm: drop microvm_gsi_handler()
microvm: make pcie irq base runtime changeable
microvm: make number of virtio transports runtime changeable
x86: add support for second ioapic
x86: rewrite gsi_handler()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw')
-rw-r--r-- | include/hw/i386/ioapic.h | 2 | ||||
-rw-r--r-- | include/hw/i386/ioapic_internal.h | 2 | ||||
-rw-r--r-- | include/hw/i386/microvm.h | 6 | ||||
-rw-r--r-- | include/hw/i386/x86.h | 3 |
4 files changed, 10 insertions, 3 deletions
diff --git a/include/hw/i386/ioapic.h b/include/hw/i386/ioapic.h index 06bfaaeac6..ef37b8a9fd 100644 --- a/include/hw/i386/ioapic.h +++ b/include/hw/i386/ioapic.h @@ -22,6 +22,8 @@ #define IOAPIC_NUM_PINS 24 #define IO_APIC_DEFAULT_ADDRESS 0xfec00000 +#define IO_APIC_SECONDARY_ADDRESS (IO_APIC_DEFAULT_ADDRESS + 0x10000) +#define IO_APIC_SECONDARY_IRQBASE 24 /* primary 0 -> 23, secondary 24 -> 47 */ #define TYPE_KVM_IOAPIC "kvm-ioapic" #define TYPE_IOAPIC "ioapic" diff --git a/include/hw/i386/ioapic_internal.h b/include/hw/i386/ioapic_internal.h index 0f9002a2c2..021e715f11 100644 --- a/include/hw/i386/ioapic_internal.h +++ b/include/hw/i386/ioapic_internal.h @@ -27,7 +27,7 @@ #include "qemu/notify.h" #include "qom/object.h" -#define MAX_IOAPICS 1 +#define MAX_IOAPICS 2 #define IOAPIC_LVT_DEST_SHIFT 56 #define IOAPIC_LVT_DEST_IDX_SHIFT 48 diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h index 0fc2160077..f25f837441 100644 --- a/include/hw/i386/microvm.h +++ b/include/hw/i386/microvm.h @@ -52,7 +52,6 @@ /* Platform virtio definitions */ #define VIRTIO_MMIO_BASE 0xfeb00000 -#define VIRTIO_NUM_TRANSPORTS 8 #define VIRTIO_CMDLINE_MAXLEN 64 #define GED_MMIO_BASE 0xfea00000 @@ -67,13 +66,13 @@ #define PCIE_MMIO_SIZE 0x20000000 #define PCIE_ECAM_BASE 0xe0000000 #define PCIE_ECAM_SIZE 0x10000000 -#define PCIE_IRQ_BASE 12 /* Machine type options */ #define MICROVM_MACHINE_PIT "pit" #define MICROVM_MACHINE_PIC "pic" #define MICROVM_MACHINE_RTC "rtc" #define MICROVM_MACHINE_PCIE "pcie" +#define MICROVM_MACHINE_IOAPIC2 "ioapic2" #define MICROVM_MACHINE_ISA_SERIAL "isa-serial" #define MICROVM_MACHINE_OPTION_ROMS "x-option-roms" #define MICROVM_MACHINE_AUTO_KERNEL_CMDLINE "auto-kernel-cmdline" @@ -92,12 +91,15 @@ struct MicrovmMachineState { OnOffAuto pit; OnOffAuto rtc; OnOffAuto pcie; + OnOffAuto ioapic2; bool isa_serial; bool option_roms; bool auto_kernel_cmdline; /* Machine state */ + uint32_t pcie_irq_base; uint32_t virtio_irq_base; + uint32_t virtio_num_transports; bool kernel_cmdline_fixed; Notifier machine_done; Notifier powerdown_req; diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index 739fac5087..3f9b052cfc 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -50,6 +50,7 @@ struct X86MachineState { ISADevice *rtc; FWCfgState *fw_cfg; qemu_irq *gsi; + DeviceState *ioapic2; GMappedFile *initrd_mapped_file; HotplugHandler *acpi_dev; @@ -120,10 +121,12 @@ bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms); typedef struct GSIState { qemu_irq i8259_irq[ISA_NUM_IRQS]; qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; + qemu_irq ioapic2_irq[IOAPIC_NUM_PINS]; } GSIState; qemu_irq x86_allocate_cpu_irq(void); void gsi_handler(void *opaque, int n, int level); void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name); +DeviceState *ioapic_init_secondary(GSIState *gsi_state); #endif |