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authorNicholas Piggin <npiggin@gmail.com>2022-08-11 19:37:26 +1000
committerDaniel Henrique Barboza <danielhb413@gmail.com>2022-08-31 14:08:05 -0300
commit0bf4d77e5922128506a3495d72ee9f432726c085 (patch)
tree6a4a33badb3da1dd1d46a17242bd91d84a744587 /include/hw
parent21d3a78ed9cf470f87180db62f7aa1296b7b0ee5 (diff)
ppc/pnv: Add initial P9/10 SBE model
The SBE (Self Boot Engine) are on-chip microcontrollers that perform early boot steps, as well as provide some runtime facilities (e.g., timer, secure register access, MPIPL). The latter facilities are accessed mostly via a message system called SBEFIFO. This driver provides initial emulation for the SBE runtime registers and a very basic SBEFIFO implementation that provides the timer command. This covers the basic SBE behaviour expected by skiboot when booting. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20220811093726.1442343-1-npiggin@gmail.com> [danielhb: fixed SBE_HOST_RESPONSE_MASK long line] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'include/hw')
-rw-r--r--include/hw/ppc/pnv.h3
-rw-r--r--include/hw/ppc/pnv_sbe.h55
-rw-r--r--include/hw/ppc/pnv_xscom.h12
3 files changed, 70 insertions, 0 deletions
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index b991194223..37c303bf36 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -27,6 +27,7 @@
#include "hw/ppc/pnv_pnor.h"
#include "hw/ppc/pnv_psi.h"
#include "hw/ppc/pnv_occ.h"
+#include "hw/ppc/pnv_sbe.h"
#include "hw/ppc/pnv_homer.h"
#include "hw/ppc/pnv_xive.h"
#include "hw/ppc/pnv_core.h"
@@ -100,6 +101,7 @@ struct Pnv9Chip {
Pnv9Psi psi;
PnvLpcController lpc;
PnvOCC occ;
+ PnvSBE sbe;
PnvHomer homer;
uint32_t nr_quads;
@@ -129,6 +131,7 @@ struct Pnv10Chip {
Pnv9Psi psi;
PnvLpcController lpc;
PnvOCC occ;
+ PnvSBE sbe;
PnvHomer homer;
uint32_t nr_quads;
diff --git a/include/hw/ppc/pnv_sbe.h b/include/hw/ppc/pnv_sbe.h
new file mode 100644
index 0000000000..f54a3ae9ba
--- /dev/null
+++ b/include/hw/ppc/pnv_sbe.h
@@ -0,0 +1,55 @@
+/*
+ * QEMU PowerPC PowerNV Emulation of some SBE behaviour
+ *
+ * Copyright (c) 2022, IBM Corporation.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef PPC_PNV_SBE_H
+#define PPC_PNV_SBE_H
+
+#include "qom/object.h"
+
+#define TYPE_PNV_SBE "pnv-sbe"
+OBJECT_DECLARE_TYPE(PnvSBE, PnvSBEClass, PNV_SBE)
+#define TYPE_PNV9_SBE TYPE_PNV_SBE "-POWER9"
+DECLARE_INSTANCE_CHECKER(PnvSBE, PNV9_SBE, TYPE_PNV9_SBE)
+#define TYPE_PNV10_SBE TYPE_PNV_SBE "-POWER10"
+DECLARE_INSTANCE_CHECKER(PnvSBE, PNV10_SBE, TYPE_PNV10_SBE)
+
+struct PnvSBE {
+ DeviceState xd;
+
+ uint64_t mbox[8];
+ uint64_t sbe_doorbell;
+ uint64_t host_doorbell;
+
+ qemu_irq psi_irq;
+ QEMUTimer *timer;
+
+ MemoryRegion xscom_mbox_regs;
+ MemoryRegion xscom_ctrl_regs;
+};
+
+struct PnvSBEClass {
+ DeviceClass parent_class;
+
+ int xscom_ctrl_size;
+ int xscom_mbox_size;
+ const MemoryRegionOps *xscom_ctrl_ops;
+ const MemoryRegionOps *xscom_mbox_ops;
+};
+
+#endif /* PPC_PNV_SBE_H */
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 7c7440de0c..c6e9ef8dd2 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -92,6 +92,12 @@ struct PnvXScomInterfaceClass {
#define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE
#define PNV9_XSCOM_OCC_SIZE 0x8000
+#define PNV9_XSCOM_SBE_CTRL_BASE 0x00050008
+#define PNV9_XSCOM_SBE_CTRL_SIZE 0x1
+
+#define PNV9_XSCOM_SBE_MBOX_BASE 0x000D0050
+#define PNV9_XSCOM_SBE_MBOX_SIZE 0x16
+
#define PNV9_XSCOM_PBA_BASE 0x5012b00
#define PNV9_XSCOM_PBA_SIZE 0x40
@@ -134,6 +140,12 @@ struct PnvXScomInterfaceClass {
#define PNV10_XSCOM_OCC_BASE PNV9_XSCOM_OCC_BASE
#define PNV10_XSCOM_OCC_SIZE PNV9_XSCOM_OCC_SIZE
+#define PNV10_XSCOM_SBE_CTRL_BASE PNV9_XSCOM_SBE_CTRL_BASE
+#define PNV10_XSCOM_SBE_CTRL_SIZE PNV9_XSCOM_SBE_CTRL_SIZE
+
+#define PNV10_XSCOM_SBE_MBOX_BASE PNV9_XSCOM_SBE_MBOX_BASE
+#define PNV10_XSCOM_SBE_MBOX_SIZE PNV9_XSCOM_SBE_MBOX_SIZE
+
#define PNV10_XSCOM_PBA_BASE 0x01010CDA
#define PNV10_XSCOM_PBA_SIZE 0x40