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authorPeter Maydell <peter.maydell@linaro.org>2019-07-22 15:16:48 +0100
committerPeter Maydell <peter.maydell@linaro.org>2019-07-22 15:16:48 +0100
commit23da9e297b4120ca9702cabec91599a44255fe96 (patch)
tree8eb09f5aa4898bbf40883f34a1be0a65e55d0036 /include/hw
parent9d2e1fcd14c2bae5be1992214a03c0ddff714c80 (diff)
parentddb45afbfbc639365d6c934e4e29f6de5e5e2a0e (diff)
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190722' into staging
target-arm queue: * target/arm: Add missing break statement for Hypervisor Trap Exception (fixes handling of SMC insn taken to AArch32 Hyp mode via HCR.TSC) * hw/arm/fsl-imx6ul.c: Remove dead SMP-related code * target/arm: Limit ID register assertions to TCG * configure: Clarify URL to source downloads * contrib/elf2dmp: Build download.o with CURL_CFLAGS # gpg: Signature made Mon 22 Jul 2019 14:13:31 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190722: contrib/elf2dmp: Build download.o with CURL_CFLAGS configure: Clarify URL to source downloads target/arm: Limit ID register assertions to TCG hw/arm/fsl-imx6ul.c: Remove dead SMP-related code target/arm: Add missing break statement for Hypervisor Trap Exception Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw')
-rw-r--r--include/hw/arm/fsl-imx6ul.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index 9e94e98f8e..eda389aec7 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -61,7 +61,7 @@ typedef struct FslIMX6ULState {
DeviceState parent_obj;
/*< public >*/
- ARMCPU cpu[FSL_IMX6UL_NUM_CPUS];
+ ARMCPU cpu;
A15MPPrivState a7mpcore;
IMXGPTState gpt[FSL_IMX6UL_NUM_GPTS];
IMXEPITState epit[FSL_IMX6UL_NUM_EPITS];