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authorGuenter Roeck <linux@roeck-us.net>2020-01-23 15:22:41 +0000
committerPeter Maydell <peter.maydell@linaro.org>2020-01-23 16:34:15 +0000
commitdab15fbe2abaca696dae45e6e22e093379ed9c05 (patch)
tree19aaf2b9818e37a64a59fc96ecdeca285359326d /include/hw
parentddf59e9ccebfce0474152db34e07efaaed417eb6 (diff)
hw/arm/exynos4210: Fix DMA initialization
First parameter to exynos4210_get_irq() is not the SPI port number, but the interrupt group number. Interrupt groups are 20 for mdma and 21 for pdma. Interrupts are not inverted. Controllers support 32 events (pdma) or 31 events (mdma). Events must all be routed to a single interrupt line. Set other parameters as documented in Exynos4210 datasheet, section 8 (DMA controller). Fixes: 59520dc65e ("hw/arm/exynos4210: Add DMA support for the Exynos4210") Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20200123052540.6132-4-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw')
-rw-r--r--include/hw/arm/exynos4210.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index f0f23b0e9b..55260394af 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -24,6 +24,7 @@
#ifndef EXYNOS4210_H
#define EXYNOS4210_H
+#include "hw/or-irq.h"
#include "hw/sysbus.h"
#include "target/arm/cpu-qom.h"
@@ -74,6 +75,8 @@
#define EXYNOS4210_I2C_NUMBER 9
+#define EXYNOS4210_NUM_DMA 3
+
typedef struct Exynos4210Irq {
qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
@@ -97,6 +100,7 @@ typedef struct Exynos4210State {
MemoryRegion boot_secondary;
MemoryRegion bootreg_mem;
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
+ qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
} Exynos4210State;
#define TYPE_EXYNOS4210_SOC "exynos4210"