diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2017-07-13 10:47:10 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-07-13 10:47:10 +0100 |
| commit | 6e2c46334385c7e295ac883c801c81b4925fb54f (patch) | |
| tree | 44ddadc2d77a47bb95e77fb5b7463792cb2e598c /include/hw | |
| parent | 31fe1c414501047cbb91b695bdccc0068496dcf6 (diff) | |
| parent | 792dac309c8660306557ba058b8b5a6a75ab3c1f (diff) | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170711' into staging
target-arm queue:
* v7M: ignore writes to CONTROL.SPSEL from Thread mode
* KVM: Enable in-kernel timers with user space gic
* aspeed: Register all watchdogs
* hw/misc: Add Exynos4210 Pseudo Random Number Generator
# gpg: Signature made Tue 11 Jul 2017 11:28:15 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20170711:
target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode
ARM: KVM: Enable in-kernel timers with user space gic
aspeed: Register all watchdogs
hw/misc: Add Exynos4210 Pseudo Random Number Generator
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/arm/aspeed_soc.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 4c5fc66a1e..0b88baaad0 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -23,6 +23,7 @@ #include "hw/net/ftgmac100.h" #define ASPEED_SPIS_NUM 2 +#define ASPEED_WDTS_NUM 3 typedef struct AspeedSoCState { /*< private >*/ @@ -39,7 +40,7 @@ typedef struct AspeedSoCState { AspeedSMCState fmc; AspeedSMCState spi[ASPEED_SPIS_NUM]; AspeedSDMCState sdmc; - AspeedWDTState wdt; + AspeedWDTState wdt[ASPEED_WDTS_NUM]; FTGMAC100State ftgmac100; } AspeedSoCState; @@ -56,6 +57,7 @@ typedef struct AspeedSoCInfo { const hwaddr *spi_bases; const char *fmc_typename; const char **spi_typename; + int wdts_num; } AspeedSoCInfo; typedef struct AspeedSoCClass { |