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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2020-10-12 14:49:54 +0200
committerPaolo Bonzini <pbonzini@redhat.com>2020-12-10 12:15:03 -0500
commit9ce89a22aed41e8486dddb27fbeea9f182b90516 (patch)
treeb70e3fedb9a886a8b4bf935b77a0db7da595209b /include/hw/ssi
parent5ade579ba9ae81adcb36b0ff185ce13cc560ed01 (diff)
hw/ssi: Update coding style to make checkpatch.pl happy
To make the next commit easier to review, clean this code first. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012124955.3409127-3-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'include/hw/ssi')
-rw-r--r--include/hw/ssi/ssi.h16
1 files changed, 9 insertions, 7 deletions
diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
index fe3028c39d..c15548425a 100644
--- a/include/hw/ssi/ssi.h
+++ b/include/hw/ssi/ssi.h
@@ -1,12 +1,14 @@
/* QEMU Synchronous Serial Interface support. */
-/* In principle SSI is a point-point interface. As such the qemu
- implementation has a single slave device on a "bus".
- However it is fairly common for boards to have multiple slaves
- connected to a single master, and select devices with an external
- chip select. This is implemented in qemu by having an explicit mux device.
- It is assumed that master and slave are both using the same transfer width.
- */
+/*
+ * In principle SSI is a point-point interface. As such the qemu
+ * implementation has a single slave device on a "bus".
+ * However it is fairly common for boards to have multiple slaves
+ * connected to a single master, and select devices with an external
+ * chip select. This is implemented in qemu by having an explicit mux device.
+ * It is assumed that master and slave are both using the same transfer
+ * width.
+ */
#ifndef QEMU_SSI_H
#define QEMU_SSI_H