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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2018-01-16 13:28:15 +0000
committerPeter Maydell <peter.maydell@linaro.org>2018-01-16 13:28:15 +0000
commitf82a0f449b2fdf314900116047ea6d9ee5a2da06 (patch)
tree38d9771b00b1d31fda83ecf471e2f9dc7787f1b5 /include/hw/sd/sdhci.h
parent8081796a75414f9ed5ec3d97158e543ed45908ec (diff)
sdhci: clean up includes
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 20180115182436.2066-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/sd/sdhci.h')
-rw-r--r--include/hw/sd/sdhci.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 0f0c3f1e64..1335373d3c 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -26,17 +26,19 @@
#define SDHCI_H
#include "qemu-common.h"
-#include "hw/block/block.h"
#include "hw/pci/pci.h"
#include "hw/sysbus.h"
#include "hw/sd/sd.h"
/* SD/MMC host controller state */
typedef struct SDHCIState {
+ /*< private >*/
union {
PCIDevice pcidev;
SysBusDevice busdev;
};
+
+ /*< public >*/
SDBus sdbus;
MemoryRegion iomem;
@@ -46,6 +48,7 @@ typedef struct SDHCIState {
qemu_irq ro_cb;
qemu_irq irq;
+ /* Registers cleared on reset */
uint32_t sdmasysad; /* SDMA System Address register */
uint16_t blksize; /* Host DMA Buff Boundary and Transfer BlkSize Reg */
uint16_t blkcnt; /* Blocks count for current transfer */
@@ -70,8 +73,10 @@ typedef struct SDHCIState {
uint16_t acmd12errsts; /* Auto CMD12 error status register */
uint64_t admasysaddr; /* ADMA System Address Register */
+ /* Read-only registers */
uint32_t capareg; /* Capabilities Register */
uint32_t maxcurr; /* Maximum Current Capabilities Register */
+
uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */
uint32_t buf_maxsz;
uint16_t data_count; /* current element in FIFO buffer */