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| author | Alistair Francis <alistair.francis@wdc.com> | 2020-04-23 10:50:09 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-06-03 09:11:51 -0700 |
| commit | 36b80ad99f7ea4979a4c5fc6e4072619b405e3b0 (patch) | |
| tree | 9ba62390cd163c7be8fae917cedeabeadf3d0160 /include/hw/riscv | |
| parent | ff832b77aa8ab454e092fb73b61821e56218e8a5 (diff) | |
target/riscv: Add the lowRISC Ibex CPU
Ibex is a small and efficient, 32-bit, in-order RISC-V core with
a 2-stage pipeline that implements the RV32IMC instruction set
architecture.
For more details on lowRISC see here:
https://github.com/lowRISC/ibex
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Diffstat (limited to 'include/hw/riscv')
0 files changed, 0 insertions, 0 deletions