diff options
| author | Alistair Francis <alistair.francis@wdc.com> | 2018-04-26 13:59:08 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2018-07-05 15:24:25 -0700 |
| commit | 5a7f76a3d47a75290868968682c0585d380764a4 (patch) | |
| tree | 7488582eb85f16f96d7287162d6adeecabf29d33 /include/hw/riscv | |
| parent | bde3ab9a9f2c2d08c7dabe77f19528b3f094b620 (diff) | |
hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device
Connect the Cadence GEM ethernet device. This also requires us to
expose the plic interrupt lines.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
Diffstat (limited to 'include/hw/riscv')
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 49f1946539..e8b4d9ffa3 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -19,6 +19,8 @@ #ifndef HW_SIFIVE_U_H #define HW_SIFIVE_U_H +#include "hw/net/cadence_gem.h" + #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" #define RISCV_U_SOC(obj) \ OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC) @@ -30,6 +32,7 @@ typedef struct SiFiveUSoCState { /*< public >*/ RISCVHartArrayState cpus; DeviceState *plic; + CadenceGEMState gem; } SiFiveUSoCState; typedef struct SiFiveUState { @@ -49,12 +52,14 @@ enum { SIFIVE_U_PLIC, SIFIVE_U_UART0, SIFIVE_U_UART1, - SIFIVE_U_DRAM + SIFIVE_U_DRAM, + SIFIVE_U_GEM }; enum { SIFIVE_U_UART0_IRQ = 3, - SIFIVE_U_UART1_IRQ = 4 + SIFIVE_U_UART1_IRQ = 4, + SIFIVE_U_GEM_IRQ = 0x35 }; enum { |