aboutsummaryrefslogtreecommitdiff
path: root/include/hw/riscv
diff options
context:
space:
mode:
authorAlistair Francis <alistair.francis@wdc.com>2018-04-26 11:15:24 -0700
committerAlistair Francis <alistair.francis@wdc.com>2018-07-05 15:24:25 -0700
commit2308092b2b78e6e083092bd3599cec6a0769319e (patch)
treeb9db2f82d94eb9d0b1012b7ca5062212502c3123 /include/hw/riscv
parentcee35138b59c6d6b0808c5fa644e3f063832860f (diff)
hw/riscv/sifive_u: Create a SiFive U SoC object
Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine. We leave the SoC, RAM, device tree and reset/fdt loading as part of the machine. All the other device creation has been moved to the SoC. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Michael Clark <mjc@sifive.com>
Diffstat (limited to 'include/hw/riscv')
-rw-r--r--include/hw/riscv/sifive_u.h16
1 files changed, 14 insertions, 2 deletions
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 94a390566e..49f1946539 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -19,13 +19,25 @@
#ifndef HW_SIFIVE_U_H
#define HW_SIFIVE_U_H
-typedef struct SiFiveUState {
+#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
+#define RISCV_U_SOC(obj) \
+ OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
+
+typedef struct SiFiveUSoCState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
- RISCVHartArrayState soc;
+ RISCVHartArrayState cpus;
DeviceState *plic;
+} SiFiveUSoCState;
+
+typedef struct SiFiveUState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ SiFiveUSoCState soc;
void *fdt;
int fdt_size;
} SiFiveUState;