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authorAlistair Francis <Alistair.Francis@wdc.com>2018-12-11 22:37:36 +0000
committerPalmer Dabbelt <palmer@sifive.com>2018-12-20 11:45:20 -0800
commit6d56e39649808696b2321cbd200dd7ccaa7ef7fe (patch)
treea5f6a72b823e0f402ffbac38bd5b5adfcce9f511 /include/hw/riscv
parentbb1973aadb78bfb653287421d9df8ade1accc4af (diff)
hw/riscv/virt: Connect the gpex PCIe
Connect the gpex PCIe device based on the device tree included in the HiFive Unleashed ROM. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Andrea Bolognani <abologna@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'include/hw/riscv')
-rw-r--r--include/hw/riscv/virt.h13
1 files changed, 12 insertions, 1 deletions
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 2b2e6dd4ea..f12deaebd6 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -38,13 +38,17 @@ enum {
VIRT_PLIC,
VIRT_UART0,
VIRT_VIRTIO,
- VIRT_DRAM
+ VIRT_DRAM,
+ VIRT_PCIE_MMIO,
+ VIRT_PCIE_PIO,
+ VIRT_PCIE_ECAM
};
enum {
UART0_IRQ = 10,
VIRTIO_IRQ = 1, /* 1 to 8 */
VIRTIO_COUNT = 8,
+ PCIE_IRQ = 0x20, /* 32 to 35 */
VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
};
@@ -62,6 +66,13 @@ enum {
#define VIRT_PLIC_CONTEXT_BASE 0x200000
#define VIRT_PLIC_CONTEXT_STRIDE 0x1000
+#define FDT_PCI_ADDR_CELLS 3
+#define FDT_PCI_INT_CELLS 1
+#define FDT_PLIC_ADDR_CELLS 0
+#define FDT_PLIC_INT_CELLS 1
+#define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \
+ FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS)
+
#if defined(TARGET_RISCV32)
#define VIRT_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
#elif defined(TARGET_RISCV64)