diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2019-09-06 09:20:02 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-09-17 08:42:46 -0700 |
| commit | 20f41c869830fdf0ac9aec8d14b766167f47ce7d (patch) | |
| tree | 81d6ea4c4356d23ae2294e1c98f6f6112b43c31d /include/hw/riscv/sifive_u.h | |
| parent | 68c9a9b3eb5897bf39e6aa0aa72e5761f3bc9725 (diff) | |
riscv: Add a sifive_cpu.h to include both E and U cpu type defines
Group SiFive E and U cpu type defines into one header file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'include/hw/riscv/sifive_u.h')
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index be021ce256..f25bad8f13 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -21,6 +21,7 @@ #include "hw/net/cadence_gem.h" #include "hw/riscv/riscv_hart.h" +#include "hw/riscv/sifive_cpu.h" #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" #define RISCV_U_SOC(obj) \ @@ -78,10 +79,4 @@ enum { #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 -#if defined(TARGET_RISCV32) -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 -#elif defined(TARGET_RISCV64) -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 -#endif - #endif |