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authorAlexander Graf <agraf@suse.de>2014-04-06 01:32:06 +0200
committerAlexander Graf <agraf@suse.de>2014-04-08 11:20:04 +0200
commite81a982aa5398269a2cc344091ffa4930bdd242f (patch)
tree5d09772f11575fffff75613be0dea2b7899c362f /include/hw/ppc/ppc.h
parent6cd7db3d92d44344d75feb432e3ece8587e1afd4 (diff)
PPC: Clean up DECR implementation
There are 3 different variants of the decrementor for BookE and BookS. The BookE variant sets TSR[DIS] to 1 when the DEC value becomes 1 or 0. TSR[DIS] is then the indicator whether the decrementor interrupt line is asserted or not. The old BookS variant treats DEC as an edge interrupt that gets triggered when the DEC value's top bit turns 1 from 0. The new BookS variant maintains the assertion bit inside DEC itself. Whenever the DEC value becomes negative (top bit set) the DEC interrupt line is asserted. So far we implemented mostly the old BookS variant. Let's do them all properly. This fixes booting pseries ppc64 guest images in TCG mode for me. Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'include/hw/ppc/ppc.h')
-rw-r--r--include/hw/ppc/ppc.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index 835418aeb0..d71bd07497 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -44,6 +44,9 @@ struct ppc_tb_t {
#define PPC_DECR_ZERO_TRIGGERED (1 << 3) /* Decr interrupt triggered when
* the decrementer reaches zero.
*/
+#define PPC_DECR_UNDERFLOW_LEVEL (1 << 4) /* Decr interrupt active when
+ * the most significant bit is 1.
+ */
uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);
clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq);