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authorCédric Le Goater <clg@kaod.org>2019-03-07 23:35:34 +0100
committerDavid Gibson <david@gibson.dropbear.id.au>2019-03-12 14:33:04 +1100
commitae85605531cde2856d0b37804dc9a32028d89a34 (patch)
tree264745ccbb72580e9e271ba6185aa83206ee0c19 /include/hw/ppc/pnv.h
parent31bc6fa7fa8124ff8fb08373f9402985c806919f (diff)
ppc/pnv: add a PSI bridge class model
To ease the introduction of the PSI bridge model for POWER9, abstract the POWER chip differences in a PnvPsi class model and introduce a specific Pnv8Psi type for POWER8. POWER8 interface to the interrupt controller is still XICS whereas POWER9 uses the new XIVE model. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190307223548.20516-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include/hw/ppc/pnv.h')
-rw-r--r--include/hw/ppc/pnv.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index eb4bba25b3..3b5f9cd531 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -71,7 +71,7 @@ typedef struct Pnv8Chip {
MemoryRegion icp_mmio;
PnvLpcController lpc;
- PnvPsi psi;
+ Pnv8Psi psi;
PnvOCC occ;
} Pnv8Chip;