diff options
| author | Nicholas Piggin <npiggin@gmail.com> | 2023-05-16 02:02:01 +1000 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2023-05-28 13:25:11 -0300 |
| commit | 277ee17212f0ac965d1fb7d65d8f938a790229ad (patch) | |
| tree | 7372b26d266c5190a3e3d9d498f1585bafc5c066 /include/hw/ppc/pnv.h | |
| parent | 03ec9d9d22bb7ec81f35c1c34249d2989e7a74b4 (diff) | |
target/ppc: Add POWER9 DD2.2 model
POWER9 DD2.1 and earlier had significant limitations when running KVM,
including lack of "mixed mode" MMU support (ability to run HPT and RPT
mode on threads of the same core), and a translation prefetch issue
which is worked around by disabling "AIL" mode for the guest.
These processors are not widely available, and it's difficult to deal
with all these quirks in qemu +/- KVM, so create a POWER9 DD2.2 CPU
and make it the default POWER9 CPU.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Message-Id: <20230515160201.394587-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'include/hw/ppc/pnv.h')
| -rw-r--r-- | include/hw/ppc/pnv.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 409f3bf763..7e5fef7c43 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -48,7 +48,7 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8, DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL, TYPE_PNV_CHIP_POWER8NVL) -#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") +#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.2") DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, TYPE_PNV_CHIP_POWER9) |