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authorAleksandr Bezzubikov <zuban32s@gmail.com>2017-08-18 02:36:48 +0300
committerMichael S. Tsirkin <mst@redhat.com>2017-09-08 16:15:17 +0300
commit70e1ee59bb9490d9ac529e96820a03b346086ca1 (patch)
tree79d1ed786bcbdefd36bb950666de67ca796191e4 /include/hw/pci
parenta35fe226558ac85436ea01af8977f1834927f53f (diff)
hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware
On PCI init PCI bridges may need some extra info about bus number, IO, memory and prefetchable memory to reserve. QEMU can provide this with a special vendor-specific PCI capability. Signed-off-by: Aleksandr Bezzubikov <zuban32s@gmail.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Tested-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include/hw/pci')
-rw-r--r--include/hw/pci/pci_bridge.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h
index ff7cbaa227..1acadc2c15 100644
--- a/include/hw/pci/pci_bridge.h
+++ b/include/hw/pci/pci_bridge.h
@@ -67,4 +67,29 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
#define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
#define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
+typedef struct PCIBridgeQemuCap {
+ uint8_t id; /* Standard PCI capability header field */
+ uint8_t next; /* Standard PCI capability header field */
+ uint8_t len; /* Standard PCI vendor-specific capability header field */
+ uint8_t type; /* Red Hat vendor-specific capability type.
+ Types are defined with REDHAT_PCI_CAP_ prefix */
+
+ uint32_t bus_res; /* Minimum number of buses to reserve */
+ uint64_t io; /* IO space to reserve */
+ uint32_t mem; /* Non-prefetchable memory to reserve */
+ /* At most one of the following two fields may be set to a value
+ * different from -1 */
+ uint32_t mem_pref_32; /* Prefetchable memory to reserve (32-bit MMIO) */
+ uint64_t mem_pref_64; /* Prefetchable memory to reserve (64-bit MMIO) */
+} PCIBridgeQemuCap;
+
+#define REDHAT_PCI_CAP_RESOURCE_RESERVE 1
+
+int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
+ uint32_t bus_reserve, uint64_t io_reserve,
+ uint32_t mem_non_pref_reserve,
+ uint32_t mem_pref_32_reserve,
+ uint64_t mem_pref_64_reserve,
+ Error **errp);
+
#endif /* QEMU_PCI_BRIDGE_H */