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authorDavid Gibson <david@gibson.dropbear.id.au>2016-10-13 10:44:34 +1100
committerDavid Gibson <david@gibson.dropbear.id.au>2016-10-16 12:03:09 +1100
commit2efff1c0dd15c8debeb1647d574bec97355cd5e6 (patch)
treefd5ef05db3e408625c9e406990b8eba040c2cce8 /include/hw/pci-host/spapr.h
parent6737d9ad79f6db657c7fc5658355aa5045dbfa2c (diff)
spapr: Adjust placement of PCI host bridge to allow > 1TiB RAM
Currently the default PCI host bridge for the 'pseries' machine type is constructed with its IO windows in the 1TiB..(1TiB + 64GiB) range in guest memory space. This means that if > 1TiB of guest RAM is specified, the RAM will collide with the PCI IO windows, causing serious problems. Problems won't be obvious until guest RAM goes a bit beyond 1TiB, because there's a little unused space at the bottom of the area reserved for PCI, but essentially this means that > 1TiB of RAM has never worked with the pseries machine type. This patch fixes this by altering the placement of PHBs on large-RAM VMs. Instead of always placing the first PHB at 1TiB, it is placed at the next 1 TiB boundary after the maximum RAM address. Technically, this changes behaviour in a migration-breaking way for existing machines with > 1TiB maximum memory, but since having > 1 TiB memory was broken anyway, this seems like a reasonable trade-off. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Laurent Vivier <lvivier@redhat.com>
Diffstat (limited to 'include/hw/pci-host/spapr.h')
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