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authorJoel Stanley <joel@jms.id.au>2021-09-20 08:50:59 +0200
committerCédric Le Goater <clg@kaod.org>2021-09-20 08:50:59 +0200
commitc5811bb3b76f8115f8ce3ccee64662a44dd061d9 (patch)
tree1404242ad8cd21a11c788b41e2ca8c76b082f19b /include/hw/misc
parentfa6d98c0608ccc1591c2c2f50d168078b8c38214 (diff)
aspeed: Emulate the AST2600A3
This is the latest revision of the ASPEED 2600 SoC. As there is no need to model multiple revisions of the same SoC for the moment, update the SCU AST2600 to model the A3 revision instead of the A1 and adapt the AST2600 SoC and machines. Reset values are taken from v8 of the datasheet. Signed-off-by: Joel Stanley <joel@jms.id.au> [ clg: - Introduced an Aspeed "ast2600-a3" SoC class - Commit log update ] Message-Id: <20210629142336.750058-3-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include/hw/misc')
-rw-r--r--include/hw/misc/aspeed_scu.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index d49bfb02fb..c14aff2bcb 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -43,6 +43,8 @@ struct AspeedSCUState {
#define AST2500_A1_SILICON_REV 0x04010303U
#define AST2600_A0_SILICON_REV 0x05000303U
#define AST2600_A1_SILICON_REV 0x05010303U
+#define AST2600_A2_SILICON_REV 0x05020303U
+#define AST2600_A3_SILICON_REV 0x05030303U
#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)