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authorPeter Delevoryas <peter@pjd.dev>2022-10-24 11:20:15 +0200
committerCédric Le Goater <clg@kaod.org>2022-10-24 11:20:15 +0200
commit3648d31fa81c4a391b8cd74e9fcd410a74f72383 (patch)
treed101baeb9afbc0a5537b1ea8756004421d4c4ccc /include/hw/i2c
parent0529245488865038344d64fff7ee05864d3d17f6 (diff)
hw/i2c/aspeed: Fix old reg slave receive
I think when Klaus ported his slave mode changes from the original patch series to the rewritten I2C module, he changed the behavior of the first byte that is received by the slave device. What's supposed to happen is that the AspeedI2CBus's slave device's i2c_event callback should run, and if the event is "send_async", then it should populate the byte buffer with the 8-bit I2C address that is being sent to. Since we only support "send_async", the lowest bit should always be 0 (indicating that the master is requesting to send data). This is the code Klaus had previously, for reference. [1] switch (event) { case I2C_START_SEND: bus->buf = bus->dev_addr << 1; bus->buf &= I2CD_BYTE_BUF_RX_MASK; bus->buf <<= I2CD_BYTE_BUF_RX_SHIFT; bus->intr_status |= (I2CD_INTR_SLAVE_ADDR_RX_MATCH | I2CD_INTR_RX_DONE); aspeed_i2c_set_state(bus, I2CD_STXD); break; [1]: https://lore.kernel.org/qemu-devel/20220331165737.1073520-4-its@irrelevant.dk/ Fixes: a8d48f59cd021b25 ("hw/i2c/aspeed: add slave device in old register mode") Signed-off-by: Peter Delevoryas <peter@pjd.dev> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Message-Id: <20220820225712.713209-2-peter@pjd.dev> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include/hw/i2c')
-rw-r--r--include/hw/i2c/aspeed_i2c.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
index 300a89b343..adc904d6c1 100644
--- a/include/hw/i2c/aspeed_i2c.h
+++ b/include/hw/i2c/aspeed_i2c.h
@@ -130,6 +130,7 @@ REG32(I2CD_CMD, 0x14) /* I2CD Command/Status */
SHARED_FIELD(M_TX_CMD, 1, 1)
SHARED_FIELD(M_START_CMD, 0, 1)
REG32(I2CD_DEV_ADDR, 0x18) /* Slave Device Address */
+ SHARED_FIELD(SLAVE_DEV_ADDR1, 0, 7)
REG32(I2CD_POOL_CTRL, 0x1C) /* Pool Buffer Control */
SHARED_FIELD(RX_COUNT, 24, 5)
SHARED_FIELD(RX_SIZE, 16, 5)