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authorJean-Christophe Dubois <jcd@tribudubois.net>2015-12-17 13:37:13 +0000
committerPeter Maydell <peter.maydell@linaro.org>2015-12-17 13:37:13 +0000
commitf1f7e4bf76ad8e88a55f3ae8fd01629669d4317b (patch)
treeba390475290c2633f1b8ecdfeadf381ac5cba2dc /include/hw/gpio
parent98557acf92977b6ecf98b4f7183a518cc47d21cc (diff)
i.MX: add support for lower and upper interrupt in GPIO.
The i.MX6 GPIO device supports 2 interrupts instead of one. * 1 for the lower 16 GPIOs. * 1 for the upper 16 GPIOs. i.MX31 and i.MX25 only support 1 interrupt for the 32 GPIOs. So we add a property to turn the behavior on when required. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1447497668-1603-1-git-send-email-jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/gpio')
-rw-r--r--include/hw/gpio/imx_gpio.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/hw/gpio/imx_gpio.h b/include/hw/gpio/imx_gpio.h
index 517b2618cb..b15a09fbca 100644
--- a/include/hw/gpio/imx_gpio.h
+++ b/include/hw/gpio/imx_gpio.h
@@ -54,8 +54,9 @@ typedef struct IMXGPIOState {
uint32_t isr;
bool has_edge_sel;
uint32_t edge_sel;
+ bool has_upper_pin_irq;
- qemu_irq irq;
+ qemu_irq irq[2];
qemu_irq output[IMX_GPIO_PIN_COUNT];
} IMXGPIOState;