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authorEdgar E. Iglesias <edgar.iglesias@amd.com>2022-04-06 18:43:03 +0100
committerPeter Maydell <peter.maydell@linaro.org>2022-04-21 11:37:03 +0100
commitd6ccfc7e6734383926fccfdb92df238761cb9423 (patch)
treeca2840af704d255c17fcabd39bda0791704a826c /include/hw/arm/xlnx-versal.h
parent369e5cb0c948b65e0845ca3394e25d757dd93206 (diff)
hw/arm: versal: Connect the CRL
Connect the CRL (Clock Reset LPD) to the Versal SoC. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Frederic Konrad <fkonrad@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20220406174303.2022038-5-edgar.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/arm/xlnx-versal.h')
-rw-r--r--include/hw/arm/xlnx-versal.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 155e8c4b8c..cbe8a19c10 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -29,6 +29,7 @@
#include "hw/nvram/xlnx-versal-efuse.h"
#include "hw/ssi/xlnx-versal-ospi.h"
#include "hw/dma/xlnx_csu_dma.h"
+#include "hw/misc/xlnx-versal-crl.h"
#include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
#define TYPE_XLNX_VERSAL "xlnx-versal"
@@ -87,6 +88,8 @@ struct Versal {
qemu_or_irq irq_orgate;
XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
} xram;
+
+ XlnxVersalCRL crl;
} lpd;
/* The Platform Management Controller subsystem. */
@@ -127,6 +130,7 @@ struct Versal {
#define VERSAL_TIMER_NS_EL1_IRQ 14
#define VERSAL_TIMER_NS_EL2_IRQ 10
+#define VERSAL_CRL_IRQ 10
#define VERSAL_UART0_IRQ_0 18
#define VERSAL_UART1_IRQ_0 19
#define VERSAL_USB0_IRQ_0 22