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authorPeter Maydell <peter.maydell@linaro.org>2019-02-28 17:35:42 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-02-28 17:35:42 +0000
commit9403bccfe3e271f04e12c8c64d306e0cff589009 (patch)
tree060b865d955534528520291bc8bb51701a818385 /include/hw/arm/armsse.h
parent21ee7686d7b63c3e58a7ccab33315a8c543c7171 (diff)
parent1c9af3a9e05c1607a36df4943f8f5393d7621a91 (diff)
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190228-1' into staging
target-arm queue: * add MHU and dual-core support to Musca boards * refactor some VFP insns to be gated by ID registers * Revert "arm: Allow system registers for KVM guests to be changed by QEMU code" * Implement ARMv8.2-FHM extension * Advertise JSCVT via HWCAP for linux-user # gpg: Signature made Thu 28 Feb 2019 11:06:55 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190228-1: linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT target/arm: Enable ARMv8.2-FHM for -cpu max target/arm: Implement VFMAL and VFMSL for aarch32 target/arm: Implement FMLAL and FMLSL for aarch64 target/arm: Add helpers for FMLAL Revert "arm: Allow system registers for KVM guests to be changed by QEMU code" target/arm: Gate "miscellaneous FP" insns by ID register field target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions hw/arm/armsse: Unify init-svtor and cpuwait handling hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR* hw/arm/iotkit-sysctl: Add SSE-200 registers hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset() target/arm/cpu: Allow init-svtor property to be set after realize hw/arm/armsse: Wire up the MHUs hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/arm/armsse.h')
-rw-r--r--include/hw/arm/armsse.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index 7ef871c7df..81e082cccf 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -95,6 +95,7 @@
#include "hw/misc/iotkit-sysctl.h"
#include "hw/misc/iotkit-sysinfo.h"
#include "hw/misc/armsse-cpuid.h"
+#include "hw/misc/armsse-mhu.h"
#include "hw/misc/unimp.h"
#include "hw/or-irq.h"
#include "hw/core/split-irq.h"
@@ -166,7 +167,7 @@ typedef struct ARMSSE {
IoTKitSysCtl sysctl;
IoTKitSysCtl sysinfo;
- UnimplementedDeviceState mhu[2];
+ ARMSSEMHU mhu[2];
UnimplementedDeviceState ppu[NUM_PPUS];
UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS];