diff options
| author | Anthony Liguori <aliguori@us.ibm.com> | 2013-07-10 10:54:16 -0500 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2013-07-10 10:54:16 -0500 |
| commit | 51455c59ddc370612f6e070d8eb0e594aaa7ef24 (patch) | |
| tree | a3044bd466cb3a548e6abad273663469bf68647a /include/exec | |
| parent | 9f9a03b9818194da39c6759d9b0cbee5d7ace4e1 (diff) | |
| parent | 91b1df8cf9e1ecaa8679c9ea8713d1e25c28e6c4 (diff) | |
Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into staging
QOM CPUState refactorings
* Fix for OpenRISCCPU subclasses
* Fix for gdbstub CPU selection
* Move linux-user CPU functions into new header
* CPUState part 10 refactoring: first_cpu, next_cpu, cpu_single_env et al.
* Fix some targets to consistently inline TCG code generation
* Centrally log CPU reset
# gpg: Signature made Wed 10 Jul 2013 07:52:39 AM CDT using RSA key ID 3E7E013F
# gpg: Can't check signature: public key not found
# By Andreas Färber (41) and others
# Via Andreas Färber
* afaerber/tags/qom-cpu-for-anthony: (43 commits)
cpu: Move reset logging to CPUState
target-ppc: Change LOG_MMU_STATE() argument to CPUState
target-i386: Change LOG_PCALL_STATE() argument to CPUState
log: Change log_cpu_state[_mask]() argument to CPUState
target-i386: Change do_smm_enter() argument to X86CPU
target-i386: Change do_interrupt_all() argument to X86CPU
target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPU
target-unicore32: Change gen_intermediate_code_internal() signature
target-sparc: Change gen_intermediate_code_internal() argument to SPARCCPU
target-sh4: Change gen_intermediate_code_internal() argument to SuperHCPU
target-s390x: Change gen_intermediate_code_internal() argument to S390CPU
target-ppc: Change gen_intermediate_code_internal() argument to PowerPCCPU
target-mips: Change gen_intermediate_code_internal() argument to MIPSCPU
target-microblaze: Change gen_intermediate_code_internal() argument types
target-m68k: Change gen_intermediate_code_internal() argument to M68kCPU
target-lm32: Change gen_intermediate_code_internal() argument to LM32CPU
target-i386: Change gen_intermediate_code_internal() argument to X86CPU
target-cris: Change gen_intermediate_code_internal() argument to CRISCPU
target-arm: Change gen_intermediate_code_internal() argument to ARMCPU
target-alpha: Change gen_intermediate_code_internal() argument to AlphaCPU
...
Diffstat (limited to 'include/exec')
| -rw-r--r-- | include/exec/cpu-all.h | 4 | ||||
| -rw-r--r-- | include/exec/cpu-defs.h | 1 |
2 files changed, 0 insertions, 5 deletions
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index e791c05c4d..5084202217 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -20,7 +20,6 @@ #define CPU_ALL_H #include "qemu-common.h" -#include "qemu/tls.h" #include "exec/cpu-common.h" #include "qemu/thread.h" @@ -357,9 +356,6 @@ CPUArchState *cpu_copy(CPUArchState *env); void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...) GCC_FMT_ATTR(2, 3); -extern CPUArchState *first_cpu; -DECLARE_TLS(CPUArchState *,cpu_single_env); -#define cpu_single_env tls_var(cpu_single_env) /* Flags for use in ENV->INTERRUPT_PENDING. diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index c4ac929875..39094b3f48 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -181,7 +181,6 @@ typedef struct CPUWatchpoint { sigjmp_buf jmp_env; \ int exception_index; \ \ - CPUArchState *next_cpu; /* next CPU sharing TB cache */ \ /* user data */ \ void *opaque; \ \ |