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authorPeter Maydell <peter.maydell@linaro.org>2014-03-11 13:20:23 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-03-11 13:20:23 +0000
commit0ca540dbaea142ec5c3e7a1d12db7139b8317f37 (patch)
tree58856f1ab0e13749b2826639ea11fa28341278d1 /include/exec
parented9b103d3e3102f17791ca53d4a8b17a3de929de (diff)
parent72c1d3af6e9c2745edfeaa71918a68bcee4b79db (diff)
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140310' into staging
target-arm queue: * implement WFE as yield (improves performance with emulated SMP) * fixes to avoid undefined behaviour shifting left into sign bit * libvixl format string fixes for 32 bit hosts * fix build error when intptr_t and tcg_target_long are different sizes (eg x32) * implement PMCCNTR register * fix incorrect setting of E bit in CPSR (broke booting under KVM on ARM) # gpg: Signature made Mon 10 Mar 2014 15:05:25 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140310: target-arm: Implement WFE as a yield operation hw/arm/musicpal: Avoid shifting left into sign bit hw/ssi/xilinx_spips.c: Avoid shifting left into sign bit hw/arm/omap1.c: Avoid shifting left into sign bit pxa2xx: Don't shift into sign bit libvixl: Fix format strings for several int64_t values target-arm: Fix intptr_t vs tcg_target_long target-arm: Implements the ARM PMCCNTR register target-arm: Fix incorrect setting of E bit in CPSR Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/exec')
-rw-r--r--include/exec/cpu-defs.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 01cd8c7a2b..66a3d46938 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -59,6 +59,7 @@ typedef uint64_t target_ulong;
#define EXCP_HLT 0x10001 /* hlt instruction reached */
#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
+#define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
#define TB_JMP_CACHE_BITS 12
#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)