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authorRichard Henderson <richard.henderson@linaro.org>2024-03-01 10:41:07 -1000
committerPeter Maydell <peter.maydell@linaro.org>2024-03-05 13:22:56 +0000
commita0ff4a879cd3198adb4213653d51a39d053ef2d6 (patch)
tree2dbb34a34b978b0e7900f6ecae30df37953c7b4a /include/exec/memattrs.h
parenta1a85a9502b5d0011320fdf490c1d6bc2f8fdc79 (diff)
accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull
Allow the target to set tlb flags to apply to all of the comparators. Remove MemTxAttrs.byte_swap, as the bit is not relevant to memory transactions, only the page mapping. Adjust target/sparc to set TLB_BSWAP directly. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301204110.656742-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/exec/memattrs.h')
-rw-r--r--include/exec/memattrs.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index afa885f983..14cdd8d582 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -52,8 +52,6 @@ typedef struct MemTxAttrs {
unsigned int memory:1;
/* Requester ID (for MSI for example) */
unsigned int requester_id:16;
- /* Invert endianness for this page */
- unsigned int byte_swap:1;
} MemTxAttrs;
/* Bus masters which don't specify any attributes will get this,