diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2023-05-05 21:55:01 +0100 |
---|---|---|
committer | Richard Henderson <richard.henderson@linaro.org> | 2023-05-11 09:53:41 +0100 |
commit | 0b3c75ad1a21574cc55b0c095a7dc21e2d27ffc8 (patch) | |
tree | 861006d476925fa726a93e85eb37dd247a3f3f9e /include/exec/cpu_ldst.h | |
parent | 9877ea05de9cdce6a5da87175d8455832f8148dc (diff) |
accel/tcg: Introduce tlb_read_idx
Instead of playing with offsetof in various places, use
MMUAccessType to index an array. This is easily defined
instead of the previous dummy padding array in the union.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'include/exec/cpu_ldst.h')
-rw-r--r-- | include/exec/cpu_ldst.h | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index c141f0394f..7c867c94c3 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -360,15 +360,31 @@ static inline void clear_helper_retaddr(void) /* Needed for TCG_OVERSIZED_GUEST */ #include "tcg/tcg.h" -static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry) +static inline target_ulong tlb_read_idx(const CPUTLBEntry *entry, + MMUAccessType access_type) { + /* Do not rearrange the CPUTLBEntry structure members. */ + QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_read) != + MMU_DATA_LOAD * TARGET_LONG_SIZE); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_write) != + MMU_DATA_STORE * TARGET_LONG_SIZE); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) != + MMU_INST_FETCH * TARGET_LONG_SIZE); + + const target_ulong *ptr = &entry->addr_idx[access_type]; #if TCG_OVERSIZED_GUEST - return entry->addr_write; + return *ptr; #else - return qatomic_read(&entry->addr_write); + /* ofs might correspond to .addr_write, so use qatomic_read */ + return qatomic_read(ptr); #endif } +static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry) +{ + return tlb_read_idx(entry, MMU_DATA_STORE); +} + /* Find the TLB index corresponding to the mmu_idx + address pair. */ static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx, target_ulong addr) |