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authorRabin Vincent <rabin@rab.in>2011-11-06 16:01:08 +0000
committerPeter Maydell <peter.maydell@linaro.org>2011-11-06 16:01:08 +0000
commit41bf234d8e35e9273290df278e2aeb88c0c50a4f (patch)
tree5f563eea221ef4b9c0b169bf53b19c084f41e22c /ia64-dis.c
parent932eacc158c064935c7bab920c88a93a629e1ca4 (diff)
arm_gic: handle banked enable bits for per-cpu interrupts
The first enable set/clear register (which controls the PPIs and SGIs) is supposed to be banked for each processor. Currently it is just handled globally and this prevents recent SMP Linux kernels from booting, because CPU0 stops receiving localtimer interrupts when CPU1 disables them locally. To fix this, allow the enable bits to be enabled per-cpu. For SPIs, always enable/disable ALL_CPU_MASK. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'ia64-dis.c')
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